video: tegra: sor: set drive current for lane4
David Pu [Tue, 26 Jan 2016 19:21:06 +0000 (11:21 -0800)]
drive current for LANE4 was not set if configured as 24bpp lvds out.
fix it by programming proper drive current register if using 24bpp out.

Bug 1724122

Change-Id: Ie2ad71ace0b4f247e007e671be828230545b15f6
Signed-off-by: David Pu <dpu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1544691
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Wayne Wang (SW-TEGRA) <waywang@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>

drivers/video/tegra/dc/sor.c
drivers/video/tegra/dc/sor_regs.h

index e5fe66b..f4992ec 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/sor.c
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -186,6 +186,7 @@ static int dbg_sor_show(struct seq_file *s, void *unused)
        DUMP_REG(NV_SOR_DC(0));
        DUMP_REG(NV_SOR_DC(1));
        DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0));
+       DUMP_REG(NV_SOR_LANE4_DRIVE_CURRENT(0));
        DUMP_REG(NV_SOR_PR(0));
        DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
        DUMP_REG(NV_SOR_POSTCURSOR(0));
@@ -1230,6 +1231,9 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
        tegra_sor_writel(sor, NV_SOR_LVDS, reg_val);
        tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
                0x40404040);
+       if (!conforming && (sor->dc->pdata->default_out->depth == 24))
+               tegra_sor_writel(sor, NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum),
+                       0x40);
 
 #if 0
        tegra_sor_write_field(sor, NV_SOR_LVDS,
index cbf4b94..8080e29 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/sor_regs.h
  *
- * Copyright (c) 2011-2013, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
 #define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2                     (43)
 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3                     (51)
 #define NV_SOR_LANE_DRIVE_CURRENT(i)                           (0x4e + (i))
+#define NV_SOR_LANE4_DRIVE_CURRENT(i)                          (0x50 + (i))
 #define NV_SOR_PR(i)                                           (0x52 + (i))
 #define NV_SOR_PR_LANE3_DP_LANE3_SHIFT                         (24)
 #define NV_SOR_PR_LANE3_DP_LANE3_MASK                          (0xff << 24)