video: tegra: camera: Fix camera broken issue
Sudhir Vyas [Wed, 27 Feb 2013 01:08:48 +0000 (17:08 -0800)]
Fix camera broken issue on main/ceres.

Bug 1243432

Change-Id: I196afd166418bc01d394d20e33f78d6a92b73193
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/204343
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
GVS: Gerrit_Virtual_Submit

arch/arm/mach-tegra/tegra14_clocks.c
drivers/video/tegra/camera/camera.c
drivers/video/tegra/camera/camera_priv_defs.h

index 8049e6d..04d2554 100644 (file)
@@ -5877,9 +5877,9 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("uartd_dbg", "serial8250.0",         "uartd", 65,    0x1c0,  408000000, mux_pllp_clkm,               MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB),
        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-       PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
-       PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    164,    0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
-       PERIPH_CLK("vi_sensor2",        "tegra_camera",         "vi_sensor2",   165,    0x658,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+       PERIPH_CLK_EX("vi",     "vi",           "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
+       PERIPH_CLK("vi_sensor", "vi",           "vi_sensor",    164,    0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+       PERIPH_CLK("vi_sensor2",        "vi",           "vi_sensor2",   165,    0x658,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  700000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
        PERIPH_CLK("msenc",     "msenc",                NULL,   60,     0x170,  600000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
@@ -5899,11 +5899,11 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0x4b8,  500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsi_clk_ops),
        PERIPH_CLK("dsi1-fixed", "tegradc.0",           "dsi-fixed",    0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
        PERIPH_CLK("dsi2-fixed", "tegradc.1",           "dsi-fixed",    0,      0,      108000000, mux_pllp_out3,       PERIPH_NO_ENB),
-       PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
-       PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0x648,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71),
-       PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-       PERIPH_CLK("cilab",     "tegra_camera",         "cilab", 144,   0x614,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
-       PERIPH_CLK("cile",      "tegra_camera",         "cile",  146,   0x61c,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("csi",       "vi",           "csi",  52,     0,      102000000, mux_pllp_out3,               0),
+       PERIPH_CLK("isp",       "vi",           "isp",  23,     0x648,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71),
+       PERIPH_CLK("csus",      "vi",           "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
+       PERIPH_CLK("cilab",     "vi",           "cilab", 144,   0x614,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
+       PERIPH_CLK("cile",      "vi",           "cile",  146,   0x61c,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
        PERIPH_CLK("dsialp",    "tegradc.0",            "dsialp", 147,  0x620,  102000000, mux_pllp_pllc_clkm,          MUX | DIV_U71),
 
        PERIPH_CLK("tsensor",   "tegra-tsensor",        NULL,   100,    0x3b8,   12000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71 | PERIPH_ON_APB),
@@ -5927,7 +5927,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("isp_sapor", "isp_sapor",            NULL,   163,    0x654,  26000000, mux_pllm_pllc_pllp_plla,      MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("hdmi_audio","hdmi_audio",           NULL,   176,    0x668,  26000000, mux_pllp_pllc_clkm,           MUX | DIV_U71 | PERIPH_NO_RESET),
        PERIPH_CLK("clk72mhz",  "clk72mhz",             NULL,   177,    0x66c,  102000000, mux_pllp3_pllc_clkm,         MUX | DIV_U71 | PERIPH_NO_RESET),
-       PERIPH_CLK("vim2_clk",  "tegra_camera",         "vim2_clk",     171,    0,      26000000, mux_clk_m,                    PERIPH_NO_RESET),
+       PERIPH_CLK("vim2_clk",  "vi",           "vim2_clk",     171,    0,      26000000, mux_clk_m,                    PERIPH_NO_RESET),
        PERIPH_CLK("vgpio",     "vgpio",                NULL,   172,    0,      26000000, mux_clk_m,                    PERIPH_NO_RESET),
 
        SHARED_CLK("avp.sclk",  "tegra-avp",            "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
@@ -5961,7 +5961,7 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("msenc.emc", "tegra_msenc",          "emc",  &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("tsec.emc",  "tegra_tsec",           "emc",  &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3",       "emc",  &tegra_clk_emc, NULL, 0, 0),
-       SHARED_CLK("camera.emc", "tegra_camera",        "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
+       SHARED_CLK("camera.emc", "vi",  "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
        SHARED_CLK("iso.emc",   "iso",                  "emc",  &tegra_clk_emc, NULL, 0, SHARED_BW),
        SHARED_CLK("floor.emc", "floor.emc",            NULL,   &tegra_clk_emc, NULL, 0, 0),
        SHARED_CLK("override.emc", "override.emc",      NULL,   &tegra_clk_emc, NULL, 0, SHARED_OVERRIDE),
index b1209c8..9fab5ca 100644 (file)
 static struct clock_data clock_init[] = {
        { CAMERA_ISP_CLK, "isp", true},
        { CAMERA_VI_CLK, "vi", true},
+#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+       { CAMERA_VI_SENSOR_CLK, "vi_sensor2", true},
+#else
        { CAMERA_VI_SENSOR_CLK, "vi_sensor", true},
+#endif
        { CAMERA_CSUS_CLK, "csus", true},
        { CAMERA_CSI_CLK, "csi", true},
        { CAMERA_EMC_CLK, "emc", true},
-#ifdef CONFIG_ARCH_TEGRA_11x_SOC
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
        { CAMERA_CILAB_CLK, "cilab", true},
-       { CAMERA_CILCD_CLK, "cilcd", true},
        { CAMERA_CILE_CLK, "cile", true},
-       { CAMERA_PLL_D2_CLK, "pll_d2", false}
+       { CAMERA_PLL_D2_CLK, "pll_d2", false},
 #endif
+#ifdef CONFIG_ARCH_TEGRA_11x_SOC
+       { CAMERA_CILCD_CLK, "cilcd", true},
+#endif
+#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+       { CAMERA_VIM2CLK_CLK, "vim2_clk", true},
+#endif
+
 };
 
 static long tegra_camera_ioctl(struct file *file,
index e10fdf1..06c9119 100644 (file)
@@ -54,10 +54,15 @@ enum {
        CAMERA_CSI_CLK,
 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
        CAMERA_CILAB_CLK,
-       CAMERA_CILCD_CLK,
        CAMERA_CILE_CLK,
        CAMERA_PLL_D2_CLK,
 #endif
+#ifdef CONFIG_ARCH_TEGRA_11x_SOC
+       CAMERA_CILCD_CLK,
+#endif
+#ifdef CONFIG_ARCH_TEGRA_14x_SOC
+       CAMERA_VIM2CLK_CLK,
+#endif
        CAMERA_CLK_MAX,
 };