gpu: nvgpu: enable use_full_comp_tag_line in gpc mmu
mheyer [Sat, 20 Feb 2016 05:31:24 +0000 (21:31 -0800)]
Also GPC MMU needs to have its PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE
control bit set.

Bug 1730611

Signed-off-by: Mathias Heyer <mheyer@nvidia.com>
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Change-Id: I01e11de066ea5487bf1d9c8c8eddbf159e4882da
Reviewed-on: http://git-master/r/1014881
(cherry picked from commit d1651bbebe1b3e46d2173dec1651b3d2f4307b40)
Reviewed-on: http://git-master/r/1017445
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gm20b/gr_gm20b.c
drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h

index e291507..f445327 100644 (file)
@@ -47,6 +47,7 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g)
        temp = gk20a_readl(g, fb_mmu_ctrl_r());
        temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
                gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
+               gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() |
                gr_gpcs_pri_mmu_ctrl_vol_fault_m() |
                gr_gpcs_pri_mmu_ctrl_comp_fault_m() |
                gr_gpcs_pri_mmu_ctrl_miss_gran_m() |
index 2fea4e8..bc1edfe 100644 (file)
@@ -3494,6 +3494,11 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
 {
        return 0x1 << 11;
 }
+static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void)
+{
+       return 0x1 << 12;
+}
+
 static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
 {
        return 0x1 << 1;