ARM: tegra: power gate bypass
Bitan Biswas [Mon, 24 Sep 2012 06:01:39 +0000 (11:01 +0530)]
CPU power gate is allowed in low level but controlled
by CPU power management code

bug 1053317

Reviewed-on: http://git-master/r/134717
(cherry picked from commit 880e46d014e955418859b18a3e5b3e213fc5f560)

Change-Id: Ifb16b468c6b7511fbf5dc688e13a6b574ceed379
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/143148
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R9f63181feb02a0ad5f081e1ab175905a37bb07b6

arch/arm/mach-tegra/powergate.c

index a6b401c..55714e2 100644 (file)
@@ -1084,32 +1084,35 @@ static bool skip_pg_check(int id, bool is_unpowergate)
         * List of T11x partition id which skip power gating
         */
        static int skip_pg_t11x_list[] = {
-               0,
-               1,
-               2,
-               3,
-               4,
-               5,
-               6,
-               7,
-               8,
-               9,
-               10,
-               11,
-               12,
-               13,
-               14,
-               15,
-               16,
-               17,
-               18,
-               19,
-               20,
-               21,
-               22,
+               /*
+                * CPU power gate enable/disable done
+                * from cpu power management code
+                */
+               TEGRA_POWERGATE_CRAIL,
+               TEGRA_POWERGATE_3D,
+               TEGRA_POWERGATE_VENC,
+               TEGRA_POWERGATE_PCIE,
+               TEGRA_POWERGATE_VDEC,
+               TEGRA_POWERGATE_L2,
+               TEGRA_POWERGATE_MPE,
+               TEGRA_POWERGATE_HEG,
+               TEGRA_POWERGATE_SATA,
+               TEGRA_POWERGATE_CELP,
+               TEGRA_POWERGATE_3D1,
+               TEGRA_POWERGATE_C0NC,
+               TEGRA_POWERGATE_C1NC,
+               TEGRA_POWERGATE_DISA,
+               TEGRA_POWERGATE_DISB,
+               TEGRA_POWERGATE_XUSBA,
+               TEGRA_POWERGATE_XUSBB,
+               TEGRA_POWERGATE_XUSBC,
        };
        int i;
 
+       /*
+        * skip unnecessary multiple calls e.g. powergate call when
+        * partition is already powered-off or vice-versa
+        */
        if ((tegra_powergate_is_powered(id) &&
                is_unpowergate) ||
                (!(tegra_powergate_is_powered(id)) &&
@@ -1121,7 +1124,7 @@ static bool skip_pg_check(int id, bool is_unpowergate)
                        (is_unpowergate) ? "un" : "");
                return true;
        }
-       /* unpowergate is needed initially for cpus */
+       /* unpowergate is allowed for all partitions */
        if (!tegra_powergate_is_powered(id) &&
                is_unpowergate) {
                pr_err("Partition %s already powered-%s unpowergating\n",