video: tegra: dc: vfilter memclient only for 2x/3x
Jon Mayo [Thu, 27 Sep 2012 23:09:40 +0000 (16:09 -0700)]
Make bandwidth and latency calculations for vfilter a Tegra 2x/3x only feature.

Bug 1055607

Change-Id: I182ce8fb3a0830532f7c8e9132d2d11119cfd009
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/139489
(cherry picked from commit ec4ad6ae4cd03dfb074ec30bc986bf2f59cb813d)
Reviewed-on: http://git-master/r/146976
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R423b02d14067b02c7a23034ea6c62e1143b6ad22

drivers/video/tegra/dc/bandwidth.c
drivers/video/tegra/dc/dc.c

index 0a631b9..f7ce1b6 100644 (file)
@@ -47,22 +47,28 @@ static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
                { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
                        TEGRA_LA_DISPLAY_0CB },
        };
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
        /* window B V-filter tap for first and second display. */
        static const enum tegra_la_id vfilter_tab[2] = {
                TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
        };
+#endif
        unsigned long bw;
 
        BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
        BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
+#endif
        BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
 
        bw = max(w->bandwidth, w->new_bandwidth);
 
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
        /* tegra_dc_get_bandwidth() treats V filter windows as double
         * bandwidth, but LA has a seperate client for V filter */
        if (w->idx == 1 && win_use_v_filter(dc, w))
                bw /= 2;
+#endif
 
        /* our bandwidth is in kbytes/sec, but LA takes MBps.
         * round up bandwidth to next 1MBps */
@@ -70,10 +76,12 @@ static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
 
 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
        tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
        /* if window B, also set the 1B client for the 2-tap V filter. */
        if (w->idx == 1)
                tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
 #endif
+#endif
 }
 
 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
@@ -149,7 +157,7 @@ static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
  * (windows_tiling ? 2 : 1)
  *
  * note:
- * (*) We use 2 tap V filter, so need double BW if use V filter
+ * (*) We use 2 tap V filter on T2x/T3x, so need double BW if use V filter
  * (*) Tiling mode on T30 and DDR3 requires double BW
  *
  * return:
@@ -177,8 +185,10 @@ static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
         * is of the luma plane's size only. */
        bpp = tegra_dc_is_yuv_planar(w->fmt) ?
                2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
-       ret = dc->mode.pclk / 1000UL * bpp / 8 * (
-               win_use_v_filter(dc, w) ? 2 : 1) *
+       ret = dc->mode.pclk / 1000UL * bpp / 8 *
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
+               (win_use_v_filter(dc, w) ? 2 : 1) *
+#endif
                dfixed_trunc(w->w) / w->out_w * (WIN_IS_TILED(w) ?
                tiled_windows_bw_multiplier : 1);
 
index 3872707..ae6c549 100644 (file)
@@ -400,7 +400,9 @@ static void _dump_regs(struct tegra_dc *dc, void *data,
        DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
        DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
        DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
        DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
+#endif
        DUMP_REG(DC_DISP_DAC_CRT_CTRL);
        DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 
@@ -1521,8 +1523,11 @@ static int tegra_dc_init(struct tegra_dc *dc)
                                      TEGRA_MC_PRIO_MED);
                tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
                                      TEGRA_MC_PRIO_MED);
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
+               /* only present on Tegra2 and 3 */
                tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
                                      TEGRA_MC_PRIO_MED);
+#endif
                tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
                                      TEGRA_MC_PRIO_HIGH);
        } else if (dc->ndev->id == 1) {
@@ -1532,8 +1537,11 @@ static int tegra_dc_init(struct tegra_dc *dc)
                                      TEGRA_MC_PRIO_MED);
                tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
                                      TEGRA_MC_PRIO_MED);
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
+               /* only present on Tegra2 and 3 */
                tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
                                      TEGRA_MC_PRIO_MED);
+#endif
                tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
                                      TEGRA_MC_PRIO_HIGH);
        }