video: tegra: dc: Move to new pre-si config
Jeff Smith [Tue, 6 Nov 2012 09:05:01 +0000 (01:05 -0800)]
Change-Id: I6ba0c4ed862536167867b5ab3364f2a053d72b29
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/161707
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

drivers/video/tegra/dc/bandwidth.c
drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dc_priv.h
drivers/video/tegra/dc/dc_priv_defs.h
drivers/video/tegra/dc/dsi.c
drivers/video/tegra/dc/ext/dev.c
drivers/video/tegra/dc/rgb.c
drivers/video/tegra/dc/window.c

index 8d389aa..ec0ba2d 100644 (file)
@@ -88,14 +88,12 @@ static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
         * round up bandwidth to next 1MBps */
        bw = bw / 1000 + 1;
 
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
        tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
        /* if window B, also set the 1B client for the 2-tap V filter. */
        if (w->idx == 1)
                tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
 #endif
-#endif
 }
 
 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
index f915eca..8fab252 100644 (file)
@@ -1208,11 +1208,10 @@ u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
                goto crc_error;
        }
 
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
-       /* TODO: Replace mdelay with code to sync VBlANK, since
-        * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
-       mdelay(TEGRA_CRC_LATCHED_DELAY);
-#endif
+       if (!tegra_platform_is_linsim())
+               /* TODO: Replace mdelay with code to sync VBlANK, since
+                * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
+               mdelay(TEGRA_CRC_LATCHED_DELAY);
 
        mutex_lock(&dc->lock);
        tegra_dc_io_start(dc);
@@ -1227,24 +1226,25 @@ crc_error:
 
 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
 {
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
        u32 val;
 
+       if (tegra_platform_is_linsim())
+               return false;
+
        val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
        if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
            return true;
-#endif
+
        return false;
 }
 
 static inline void enable_dc_irq(const struct tegra_dc *dc)
 {
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
-       enable_irq(dc->irq);
-#else
-       /* Always disable DC interrupts on FPGA. */
-       disable_irq(dc->irq);
-#endif
+       if (tegra_platform_is_fpga())
+               /* Always disable DC interrupts on FPGA. */
+               disable_irq(dc->irq);
+       else
+               enable_irq(dc->irq);
 }
 
 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
@@ -1425,7 +1425,7 @@ static void tegra_dc_underflow_handler(struct tegra_dc *dc)
        /* Clear the underflow mask now that we've checked it. */
        tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
        dc->underflow_mask = 0;
-       tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
+       tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
        trace_underflow(dc);
 }
 
@@ -1474,7 +1474,6 @@ static void tegra_dc_vpulse2(struct work_struct *work)
 }
 #endif
 
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
 {
        /* pending user vblank, so wakeup */
@@ -1543,17 +1542,18 @@ bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
                        != div_s64((old_ts - dc->frame_end_timestamp),
                                dc->frametime_ns)));
 }
-#endif
 
 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
 {
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
        struct tegra_dc *dc = ptr;
        unsigned long status;
        unsigned long underflow_mask;
        u32 val;
        int need_disable = 0;
 
+       if (tegra_platform_is_fpga())
+               return IRQ_NONE;
+
        mutex_lock(&dc->lock);
        if (!dc->enabled) {
                mutex_unlock(&dc->lock);
@@ -1577,9 +1577,9 @@ static irqreturn_t tegra_dc_irq(int irq, void *ptr)
 
        /* clear all status flags except underflow, save those for the worker */
        status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
-       tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
+       tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
        val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
-       tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
+       tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
 
        /*
         * Overlays can get thier internal state corrupted during and underflow
@@ -1587,7 +1587,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *ptr)
         * if we get 4 consecutive frames with underflows, assume we're
         * hosed and reset.
         */
-       underflow_mask = status & ALL_UF_INT;
+       underflow_mask = status & ALL_UF_INT();
 
        /* Check underflow */
        if (underflow_mask) {
@@ -1614,9 +1614,6 @@ static irqreturn_t tegra_dc_irq(int irq, void *ptr)
        if (need_disable)
                tegra_dc_disable(dc);
        return IRQ_HANDLED;
-#else /* CONFIG_TEGRA_FPGA_PLATFORM */
-       return IRQ_NONE;
-#endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
 }
 
 void tegra_dc_set_color_control(struct tegra_dc *dc)
@@ -1765,13 +1762,13 @@ static int tegra_dc_init(struct tegra_dc *dc)
        tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
 #endif
        /* enable interrupts for vblank, frame_end and underflows */
-       int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
+       int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
        /* for panels with one-shot mode enable tearing effect interrupt */
        if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
                int_enable |= MSF_INT;
 
        tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
-       tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
+       tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
        tegra_dc_init_vpulse2_int(dc);
 
        tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
@@ -1898,10 +1895,10 @@ static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
        msleep(5);
        tegra_periph_reset_assert(dc->clk);
        msleep(2);
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
-       tegra_periph_reset_deassert(dc->clk);
-       msleep(1);
-#endif
+       if (tegra_platform_is_silicon()) {
+               tegra_periph_reset_deassert(dc->clk);
+               msleep(1);
+       }
 
        if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
                enable_dc_irq(tegra_dcs[1]);
@@ -2688,10 +2685,9 @@ static void tegra_dc_shutdown(struct platform_device *ndev)
        if (!dc || !dc->enabled)
                return;
 
-#ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
        /* Hack: no windows blanking for simulation to save shutdown time */
-       tegra_dc_blank(dc);
-#endif
+       if (!tegra_platform_is_linsim())
+               tegra_dc_blank(dc);
        tegra_dc_disable(dc);
 }
 
index c5cc84a..a623ae6 100644 (file)
@@ -201,11 +201,10 @@ static inline void tegra_dc_restore_interrupt(struct tegra_dc *dc, u32 val)
 
 static inline unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
 {
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
+       if (!tegra_platform_is_silicon())
+               return dc->mode.pclk;
+
        return clk_get_rate(dc->clk);
-#else
-       return dc->mode.pclk;
-#endif
 }
 
 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
index 408c2bb..e8b135a 100644 (file)
@@ -33,6 +33,7 @@
 #include <mach/dc.h>
 
 #include <mach/tegra_dc_ext.h>
+#include <mach/hardware.h>
 #include <mach/clk.h>
 
 #include "dc_reg.h"
 #define CURSOR_CLIP_SHIFT_BITS(win)    (win << 29)
 #define CURSOR_CLIP_GET_WINDOW(reg)    ((reg >> 29) & 3)
 
-#ifndef CONFIG_TEGRA_FPGA_PLATFORM
-#define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
+static inline u32 ALL_UF_INT(void)
+{
+       if (tegra_platform_is_fpga())
+               return 0;
+       return WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
+}
+
+#if defined(CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
+#define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * CONFIG_TEGRA_EMC_TO_DDR_CLOCK)
 #else
-/* ignore underflows when on simulation and fpga platform */
-#define ALL_UF_INT (0)
+#define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2)
 #endif
 
 struct tegra_dc;
index 1baeab9..6b99ba0 100644 (file)
@@ -821,11 +821,9 @@ static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
                                struct dsi_phy_timing_inclk *phy_timing_clk,
                                u32 clk_ns, u8 lphs)
 {
-       if (!(dsi->info.ganged_type)) {
-#ifndef CONFIG_TEGRA_SILICON_PLATFORM
+       if (tegra_platform_is_fpga() && !(dsi->info.ganged_type)) {
                clk_ns = (1000 * 1000) / (dsi->info.fpga_freq_khz ?
                        dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
-#endif
        }
 
        phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
@@ -855,11 +853,10 @@ static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
                ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
                ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
 
-#ifndef CONFIG_TEGRA_SILICON_PLATFORM
-       clk_ns = dsi->info.fpga_freq_khz ?
-               ((1000 * 1000) / dsi->info.fpga_freq_khz) :
-               DEFAULT_FPGA_FREQ_KHZ;
-#endif
+       if (tegra_platform_is_fpga())
+               clk_ns = dsi->info.fpga_freq_khz ?
+                       ((1000 * 1000) / dsi->info.fpga_freq_khz) :
+                       DEFAULT_FPGA_FREQ_KHZ;
 
        err = CHECK_RANGE(
        DSI_CONVERT_T_PHY_TO_T_PHY_NS(
@@ -1123,8 +1120,7 @@ static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
        tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
                                        dsi->current_bit_clk_ns, lphs);
 
-       if (dsi->info.ganged_type) {
-#ifndef CONFIG_TEGRA_SILICON_PLATFORM
+       if (tegra_platform_is_fpga() && dsi->info.ganged_type) {
                phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
                phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
                phy_timing.t_datzero += T_DATZERO_HW_INC;
@@ -1142,7 +1138,6 @@ static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
                phy_timing.t_taget += T_TAGET_HW_INC;
                phy_timing.t_tasure += T_TASURE_HW_INC;
                phy_timing.t_tago += T_TAGO_HW_INC;
-#endif
        }
        val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
                        DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
@@ -1751,11 +1746,11 @@ static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
                                dsi->shift_clk_div.div) * 2 /
                                dsi->shift_clk_div.div;
 
-#ifndef CONFIG_TEGRA_SILICON_PLATFORM
-       shift_clk_div_register = 1;
-       if (dsi->info.ganged_type)
-               shift_clk_div_register = 0;
-#endif
+       if (tegra_platform_is_fpga()) {
+               shift_clk_div_register = 1;
+               if (dsi->info.ganged_type)
+                       shift_clk_div_register = 0;
+       }
 
        val = PIXEL_CLK_DIVIDER_PCD1 |
                SHIFT_CLK_DIVIDER(shift_clk_div_register + 2);
index b1d1f5b..867a49c 100644 (file)
@@ -217,10 +217,7 @@ static int tegra_dc_ext_set_windowattr(struct tegra_dc_ext *ext,
 {
        int err = 0;
        struct tegra_dc_ext_win *ext_win = &ext->win[win->idx];
-#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM) && \
-       !defined(CONFIG_TEGRA_FPGA_PLATFORM)
        s64 timestamp_ns;
-#endif
 
        if (flip_win->handle[TEGRA_DC_Y] == NULL) {
                win->flags = 0;
@@ -290,18 +287,19 @@ static int tegra_dc_ext_set_windowattr(struct tegra_dc_ext *ext,
        if (err < 0)
                return err;
 
-#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM) && \
-       !defined(CONFIG_TEGRA_FPGA_PLATFORM)
-       timestamp_ns = timespec_to_ns(&flip_win->attr.timestamp);
+       if (tegra_platform_is_silicon()) {
+               timestamp_ns = timespec_to_ns(&flip_win->attr.timestamp);
 
-       if (timestamp_ns) {
-               /* XXX: Should timestamping be overridden by "no_vsync" flag */
-               tegra_dc_config_frame_end_intr(win->dc, true);
-               err = wait_event_interruptible(win->dc->timestamp_wq,
+               if (timestamp_ns) {
+                       /* XXX: Should timestamping be overridden by "no_vsync"
+                        * flag */
+                       tegra_dc_config_frame_end_intr(win->dc, true);
+                       err = wait_event_interruptible(win->dc->timestamp_wq,
                                tegra_dc_is_within_n_vsync(win->dc, timestamp_ns));
-               tegra_dc_config_frame_end_intr(win->dc, false);
+                       tegra_dc_config_frame_end_intr(win->dc, false);
+               }
        }
-#endif
+
        return err;
 }
 
@@ -358,12 +356,9 @@ static void tegra_dc_ext_flip_worker(struct work_struct *work)
                int index = flip_win->attr.index;
                struct tegra_dc_win *win;
                struct tegra_dc_ext_win *ext_win;
-#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM) && \
-       !defined(CONFIG_TEGRA_FPGA_PLATFORM)
                struct tegra_dc_ext_flip_data *temp = NULL;
                s64 head_timestamp = 0;
                int j = 0;
-#endif
 
                if (index < 0)
                        continue;
@@ -376,10 +371,10 @@ static void tegra_dc_ext_flip_worker(struct work_struct *work)
                        skip_flip = true;
 
                mutex_lock(&ext_win->queue_lock);
-#if !defined(CONFIG_TEGRA_SIMULATION_PLATFORM) && \
-       !defined(CONFIG_TEGRA_FPGA_PLATFORM)
                list_for_each_entry(temp, &ext_win->timestamp_queue,
                                timestamp_node) {
+                       if (!tegra_platform_is_silicon())
+                               continue;
                        if (j == 0) {
                                if (unlikely(temp != data))
                                        dev_err(&win->dc->ndev->dev,
@@ -398,7 +393,6 @@ static void tegra_dc_ext_flip_worker(struct work_struct *work)
                        }
                        j++;
                }
-#endif
                if (!list_empty(&ext_win->timestamp_queue))
                        list_del(&data->timestamp_node);
                mutex_unlock(&ext_win->queue_lock);
index fbd6ff1..c5035b4 100644 (file)
@@ -57,14 +57,7 @@ static const u32 tegra_dc_rgb_enable_out_sel_pintable[] = {
        DC_COM_PIN_OUTPUT_SELECT0,      0x00000000,
        DC_COM_PIN_OUTPUT_SELECT1,      0x00000000,
        DC_COM_PIN_OUTPUT_SELECT2,      0x00000000,
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
        DC_COM_PIN_OUTPUT_SELECT3,      0x00000000,
-#else
-       /* The display panel sub-board used on FPGA platforms (panel 86)
-          is non-standard. It expects the Data Enable signal on the WR
-          pin instead of the DE pin. */
-       DC_COM_PIN_OUTPUT_SELECT3,      0x00200000,
-#endif
        DC_COM_PIN_OUTPUT_SELECT4,      0x00210222,
        DC_COM_PIN_OUTPUT_SELECT5,      0x00002200,
        DC_COM_PIN_OUTPUT_SELECT6,      0x00020000,
@@ -115,6 +108,12 @@ static void tegra_dc_rgb_enable(struct tegra_dc *dc)
        memcpy(out_sel_pintable, tegra_dc_rgb_enable_out_sel_pintable,
                sizeof(tegra_dc_rgb_enable_out_sel_pintable));
 
+       /* The display panel sub-board used on FPGA platforms (panel 86)
+          is non-standard. It expects the Data Enable signal on the WR
+          pin instead of the DE pin. */
+       if (tegra_platform_is_fpga())
+               out_sel_pintable[3*2+1] = 0x00200000;
+
        if (dc->out && dc->out->out_sel_configs) {
                u8 *out_sels = dc->out->out_sel_configs;
                for (i = 0; i < dc->out->n_out_sel_configs; i++) {
index dfbcdba..7433bee 100644 (file)
@@ -213,15 +213,14 @@ int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
                return -EFAULT;
 
        trace_sync_windows(windows[0]->dc);
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
-       /* Don't want to timeout on simulator */
-       ret = wait_event_interruptible(windows[0]->dc->wq,
-               tegra_dc_windows_are_clean(windows, n));
-#else
-       ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
-               tegra_dc_windows_are_clean(windows, n),
-               HZ);
-#endif
+       if (tegra_platform_is_linsim())
+               /* Don't want to timeout on simulator */
+               ret = wait_event_interruptible(windows[0]->dc->wq,
+                       tegra_dc_windows_are_clean(windows, n));
+       else
+               ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
+                       tegra_dc_windows_are_clean(windows, n),
+                       HZ);
        /* tegra_dc_io_start() done in update_windows */
        tegra_dc_io_end(windows[0]->dc);
        return ret;
@@ -522,14 +521,14 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
        if (!no_vsync) {
                set_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
                tegra_dc_unmask_interrupt(dc,
-                       FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
+                       FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
                set_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
                tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
 #endif
        } else {
                clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
-               tegra_dc_mask_interrupt(dc, V_BLANK_INT | ALL_UF_INT);
+               tegra_dc_mask_interrupt(dc, V_BLANK_INT | ALL_UF_INT());
 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
                clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
                tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
@@ -568,19 +567,19 @@ void tegra_dc_trigger_windows(struct tegra_dc *dc)
 
        val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
        for (i = 0; i < DC_N_WINDOWS; i++) {
-#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
-               /* FIXME: this is not needed when the simulator
-                  clears WIN_x_UPDATE bits as in HW */
-               dc->windows[i].dirty = 0;
-               completed = 1;
-#else
-               if (!(val & (WIN_A_ACT_REQ << i))) {
+               if (tegra_platform_is_linsim()) {
+                       /* FIXME: this is not needed when the simulator
+                        * clears WIN_x_UPDATE bits as in HW */
                        dc->windows[i].dirty = 0;
                        completed = 1;
                } else {
-                       dirty = 1;
+                       if (!(val & (WIN_A_ACT_REQ << i))) {
+                               dc->windows[i].dirty = 0;
+                               completed = 1;
+                       } else {
+                               dirty = 1;
+                       }
                }
-#endif
        }
 
        if (!dirty) {