video: tegra: host: gk20a: add AELPG headers
Prashant Malani [Thu, 5 Dec 2013 22:03:05 +0000 (14:03 -0800)]
Enabling adaptive elpg is needed for the data corruption
issues seen as per the bug reported below.
Bug 1458353

Change-Id: Ie285e7e7e3849e0b8cb263a67a5dfe7056150d51
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/338872
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
(cherry picked from commit b0b937165d49e3f57fa25815239e2a0f6f155527)
Reviewed-on: http://git-master/r/394409
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prabhu Kuttiyam <pkuttiyam@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

drivers/video/tegra/host/gk20a/pmu_gk20a.h

index 39fc84c..aa6098f 100644 (file)
 
 #define ZBC_MASK(i)                    (~(~(0) << ((i)+1)) & 0xfffe)
 
-enum
-{
+/* PMU Command/Message Interfaces for Adaptive Power */
+/* Macro to get Histogram index */
+#define PMU_AP_HISTOGRAM(idx)          (idx)
+#define PMU_AP_HISTOGRAM_CONT          (4)
+
+/* Total number of histogram bins */
+#define PMU_AP_CFG_HISTOGRAM_BIN_N     (16)
+
+/* Mapping between Idle counters and histograms */
+#define PMU_AP_IDLE_MASK_HIST_IDX_0            (2)
+#define PMU_AP_IDLE_MASK_HIST_IDX_1            (3)
+#define PMU_AP_IDLE_MASK_HIST_IDX_2            (5)
+#define PMU_AP_IDLE_MASK_HIST_IDX_3            (6)
+
+
+/* Mapping between AP_CTRLs and Histograms */
+#define PMU_AP_HISTOGRAM_IDX_GRAPHICS  (PMU_AP_HISTOGRAM(1))
+
+/* Mapping between AP_CTRLs and Idle counters */
+#define PMU_AP_IDLE_MASK_GRAPHICS      (PMU_AP_IDLE_MASK_HIST_IDX_1)
+
+/* Adaptive Power Controls (AP_CTRL) */
+enum {
+       PMU_AP_CTRL_ID_GRAPHICS = 0x0,
+       /* PMU_AP_CTRL_ID_MS         ,*/
+       PMU_AP_CTRL_ID_MAX           ,
+};
+
+/* AP_CTRL Statistics */
+struct pmu_ap_ctrl_stat {
+       /*
+        * Represents whether AP is active or not
+        * TODO: This is NvBool in RM; is that 1 byte of 4 bytes?
+        */
+       u8      b_active;
+
+       /* Idle filter represented by histogram bin index */
+       u8      idle_filter_x;
+       u8      rsvd[2];
+
+       /* Total predicted power saving cycles. */
+       s32     power_saving_h_cycles;
+
+       /* Counts how many times AP gave us -ve power benefits. */
+       u32     bad_decision_count;
+
+       /*
+        * Number of times ap structure needs to skip AP iterations
+        * KICK_CTRL from kernel updates this parameter.
+        */
+       u32     skip_count;
+       u8      bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
+};
+
+/* Parameters initialized by INITn APCTRL command */
+struct pmu_ap_ctrl_init_params {
+       /* Minimum idle filter value in Us */
+       u32     min_idle_filter_us;
+
+       /*
+        * Minimum Targeted Saving in Us. AP will update idle thresholds only
+        * if power saving achieved by updating idle thresholds is greater than
+        * Minimum targeted saving.
+        */
+       u32     min_target_saving_us;
+
+       /* Minimum targeted residency of power feature in Us */
+       u32     power_break_even_us;
+
+       /*
+        * Maximum number of allowed power feature cycles per sample.
+        *
+        * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
+        * AKA pgPerSampleMax in original algorithm.
+        */
+       u32     cycles_per_sample_max;
+};
+
+/* AP Commands/Message structures */
+
+/*
+ * Structure for Generic AP Commands
+ */
+struct pmu_ap_cmd_common {
+       u8      cmd_type;
+       u16     cmd_id;
+};
+
+/*
+ * Structure for INIT AP command
+ */
+struct pmu_ap_cmd_init {
+       u8      cmd_type;
+       u16     cmd_id;
+       u8      rsvd;
+       u32     pg_sampling_period_us;
+};
+
+/*
+ * Structure for Enable/Disable ApCtrl Commands
+ */
+struct pmu_ap_cmd_enable_ctrl {
+       u8      cmd_type;
+       u16     cmd_id;
+
+       u8      ctrl_id;
+};
+
+struct pmu_ap_cmd_disable_ctrl {
+       u8      cmd_type;
+       u16     cmd_id;
+
+       u8      ctrl_id;
+};
+
+/*
+ * Structure for INIT command
+ */
+struct pmu_ap_cmd_init_ctrl {
+       u8                              cmd_type;
+       u16                             cmd_id;
+       u8                              ctrl_id;
+       struct pmu_ap_ctrl_init_params  params;
+};
+
+struct pmu_ap_cmd_init_and_enable_ctrl {
+       u8                              cmd_type;
+       u16                             cmd_id;
+       u8                              ctrl_id;
+       struct pmu_ap_ctrl_init_params  params;
+};
+
+/*
+ * Structure for KICK_CTRL command
+ */
+struct pmu_ap_cmd_kick_ctrl {
+       u8      cmd_type;
+       u16     cmd_id;
+       u8      ctrl_id;
+
+       u32     skip_count;
+};
+
+/*
+ * Structure for PARAM command
+ */
+struct pmu_ap_cmd_param {
+       u8      cmd_type;
+       u16     cmd_id;
+       u8      ctrl_id;
+
+       u32     data;
+};
+
+/*
+ * Defines for AP commands
+ */
+enum {
+       PMU_AP_CMD_ID_INIT = 0x0          ,
+       PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
+       PMU_AP_CMD_ID_ENABLE_CTRL         ,
+       PMU_AP_CMD_ID_DISABLE_CTRL        ,
+       PMU_AP_CMD_ID_KICK_CTRL           ,
+};
+
+/*
+ * AP Command
+ */
+union pmu_ap_cmd {
+       u8                                      cmd_type;
+       struct pmu_ap_cmd_common                cmn;
+       struct pmu_ap_cmd_init                  init;
+       struct pmu_ap_cmd_init_and_enable_ctrl  init_and_enable_ctrl;
+       struct pmu_ap_cmd_enable_ctrl           enable_ctrl;
+       struct pmu_ap_cmd_disable_ctrl          disable_ctrl;
+       struct pmu_ap_cmd_kick_ctrl             kick_ctrl;
+};
+
+/*
+ * Structure for generic AP Message
+ */
+struct pmu_ap_msg_common {
+       u8      msg_type;
+       u16     msg_id;
+};
+
+/*
+ * Structure for INIT_ACK Message
+ */
+struct pmu_ap_msg_init_ack {
+       u8      msg_type;
+       u16     msg_id;
+       u8      ctrl_id;
+       u32     stats_dmem_offset;
+};
+
+/*
+ * Defines for AP messages
+ */
+enum {
+       PMU_AP_MSG_ID_INIT_ACK = 0x0,
+};
+
+/*
+ * AP Message
+ */
+union pmu_ap_msg {
+       u8                              msg_type;
+       struct pmu_ap_msg_common        cmn;
+       struct pmu_ap_msg_init_ack      init_ack;
+};
+
+/* Default Sampling Period of AELPG */
+#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US                    (1000000)
+
+/* Default values of APCTRL parameters */
+#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US                   (100)
+#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US                 (10000)
+#define APCTRL_POWER_BREAKEVEN_DEFAULT_US                       (2000)
+#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT                    (100)
+
+/*
+ * Disable reason for Adaptive Power Controller
+ */
+enum {
+       APCTRL_DISABLE_REASON_RM_UNLOAD,
+       APCTRL_DISABLE_REASON_RMCTRL,
+};
+
+/*
+ * Adaptive Power Controller
+ */
+struct ap_ctrl {
+       u32                     stats_dmem_offset;
+       u32                     disable_reason_mask;
+       struct pmu_ap_ctrl_stat stat_cache;
+       u8                      b_ready;
+};
+
+/*
+ * Adaptive Power structure
+ *
+ * ap structure provides generic infrastructure to make any power feature
+ * adaptive.
+ */
+struct pmu_ap {
+       u32                     supported_mask;
+       struct ap_ctrl          ap_ctrl[PMU_AP_CTRL_ID_MAX];
+};
+
+
+enum {
        GK20A_PMU_DMAIDX_UCODE          = 0,
        GK20A_PMU_DMAIDX_VIRT           = 1,
        GK20A_PMU_DMAIDX_PHYS_VID       = 2,
@@ -237,6 +487,7 @@ struct pmu_pg_msg {
                struct pmu_pg_msg_stat stat;
                struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
                /* TBD: other pg messages */
+               union pmu_ap_msg ap_msg;
        };
 };
 
@@ -318,6 +569,7 @@ struct pmu_pg_cmd {
                struct pmu_pg_cmd_eng_buf_load eng_buf_load;
                struct pmu_pg_cmd_stat stat;
                /* TBD: other pg commands */
+               union pmu_ap_cmd ap_cmd;
        };
 };