xtensa: add support for the XTFPGA boards
Max Filippov [Mon, 5 Nov 2012 03:37:14 +0000 (07:37 +0400)]
The Avnet LX60/LX110/LX200 board is an FPGA board that can be configured with
an Xtensa processor and an OpenCores Ethernet device.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

arch/xtensa/Kconfig
arch/xtensa/Makefile
arch/xtensa/boot/Makefile
arch/xtensa/platforms/xtfpga/Makefile [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/include/platform/hardware.h [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/include/platform/lcd.h [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/include/platform/serial.h [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/lcd.c [new file with mode: 0644]
arch/xtensa/platforms/xtfpga/setup.c [new file with mode: 0644]

index 8ceb5b2..73d34e7 100644 (file)
@@ -151,6 +151,15 @@ config XTENSA_PLATFORM_S6105
        select SERIAL_CONSOLE
        select NO_IOPORT
 
+config XTENSA_PLATFORM_XTFPGA
+       bool "XTFPGA"
+       select SERIAL_CONSOLE
+       select ETHOC
+       select XTENSA_CALIBRATE_CCOUNT
+       help
+         XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
+         This hardware is capable of running a full Linux distribution.
+
 endchoice
 
 
index 227f658..7e0ae8f 100644 (file)
@@ -38,6 +38,7 @@ endif
 platform-$(CONFIG_XTENSA_PLATFORM_XT2000)      := xt2000
 platform-$(CONFIG_XTENSA_PLATFORM_ISS)         := iss
 platform-$(CONFIG_XTENSA_PLATFORM_S6105)       := s6105
+platform-$(CONFIG_XTENSA_PLATFORM_XTFPGA)      := xtfpga
 
 PLATFORM = $(platform-y)
 export PLATFORM
index cb5ff4d..196bc3c 100644 (file)
@@ -23,6 +23,7 @@ subdir-y      := lib
 
 bootdir-$(CONFIG_XTENSA_PLATFORM_ISS)   += boot-elf
 bootdir-$(CONFIG_XTENSA_PLATFORM_XT2000) += boot-redboot boot-elf boot-uboot
+bootdir-$(CONFIG_XTENSA_PLATFORM_XTFPGA) += boot-redboot boot-elf boot-uboot
 
 
 BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o
diff --git a/arch/xtensa/platforms/xtfpga/Makefile b/arch/xtensa/platforms/xtfpga/Makefile
new file mode 100644 (file)
index 0000000..b9ae206
--- /dev/null
@@ -0,0 +1,9 @@
+# Makefile for the Tensilica xtavnet Emulation Board
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+# Note 2! The CFLAGS definitions are in the main makefile...
+
+obj-y                  = setup.o lcd.o
diff --git a/arch/xtensa/platforms/xtfpga/include/platform/hardware.h b/arch/xtensa/platforms/xtfpga/include/platform/hardware.h
new file mode 100644 (file)
index 0000000..4416773
--- /dev/null
@@ -0,0 +1,69 @@
+/*
+ * arch/xtensa/platform/xtavnet/include/platform/hardware.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2006 Tensilica Inc.
+ */
+
+/*
+ * This file contains the hardware configuration of the XTAVNET boards.
+ */
+
+#ifndef __XTENSA_XTAVNET_HARDWARE_H
+#define __XTENSA_XTAVNET_HARDWARE_H
+
+/* By default NO_IRQ is defined to 0 in Linux, but we use the
+   interrupt 0 for UART... */
+#define NO_IRQ                 -1
+
+/* Memory configuration. */
+
+#define PLATFORM_DEFAULT_MEM_START 0x00000000
+#define PLATFORM_DEFAULT_MEM_SIZE  0x04000000
+
+/* Interrupt configuration. */
+
+#define PLATFORM_NR_IRQS       10
+
+/* Default assignment of LX60 devices to external interrupts. */
+
+#ifdef CONFIG_ARCH_HAS_SMP
+#define DUART16552_INTNUM      XCHAL_EXTINT3_NUM
+#define OETH_IRQ               XCHAL_EXTINT4_NUM
+#else
+#define DUART16552_INTNUM      XCHAL_EXTINT0_NUM
+#define OETH_IRQ               XCHAL_EXTINT1_NUM
+#endif
+
+/*
+ *  Device addresses and parameters.
+ */
+
+/* UART */
+#define DUART16552_PADDR       (XCHAL_KIO_PADDR + 0x0D050020)
+/* LCD instruction and data addresses. */
+#define LCD_INSTR_ADDR         ((char *)IOADDR(0x0D040000))
+#define LCD_DATA_ADDR          ((char *)IOADDR(0x0D040004))
+
+/* Misc. */
+#define XTFPGA_FPGAREGS_VADDR  IOADDR(0x0D020000)
+/* Clock frequency in Hz (read-only):  */
+#define XTFPGA_CLKFRQ_VADDR    (XTFPGA_FPGAREGS_VADDR + 0x04)
+/* Setting of 8 DIP switches:  */
+#define DIP_SWITCHES_VADDR     (XTFPGA_FPGAREGS_VADDR + 0x0C)
+/* Software reset (write 0xdead):  */
+#define XTFPGA_SWRST_VADDR     (XTFPGA_FPGAREGS_VADDR + 0x10)
+
+/*  OpenCores Ethernet controller:  */
+                               /* regs + RX/TX descriptors */
+#define OETH_REGS_PADDR                (XCHAL_KIO_PADDR + 0x0D030000)
+#define OETH_REGS_SIZE         0x1000
+#define OETH_SRAMBUFF_PADDR    (XCHAL_KIO_PADDR + 0x0D800000)
+
+                               /* 5*rx buffs + 5*tx buffs */
+#define OETH_SRAMBUFF_SIZE     (5 * 0x600 + 5 * 0x600)
+
+#endif /* __XTENSA_XTAVNET_HARDWARE_H */
diff --git a/arch/xtensa/platforms/xtfpga/include/platform/lcd.h b/arch/xtensa/platforms/xtfpga/include/platform/lcd.h
new file mode 100644 (file)
index 0000000..0e43564
--- /dev/null
@@ -0,0 +1,20 @@
+/*
+ * arch/xtensa/platform/xtavnet/include/platform/lcd.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001, 2006 Tensilica Inc.
+ */
+
+#ifndef __XTENSA_XTAVNET_LCD_H
+#define __XTENSA_XTAVNET_LCD_H
+
+/* Display string STR at position POS on the LCD. */
+void lcd_disp_at_pos(char *str, unsigned char pos);
+
+/* Shift the contents of the LCD display left or right. */
+void lcd_shiftleft(void);
+void lcd_shiftright(void);
+#endif
diff --git a/arch/xtensa/platforms/xtfpga/include/platform/serial.h b/arch/xtensa/platforms/xtfpga/include/platform/serial.h
new file mode 100644 (file)
index 0000000..14d8f7b
--- /dev/null
@@ -0,0 +1,18 @@
+/*
+ * arch/xtensa/platform/xtavnet/include/platform/serial.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001, 2006 Tensilica Inc.
+ */
+
+#ifndef __ASM_XTENSA_XTAVNET_SERIAL_H
+#define __ASM_XTENSA_XTAVNET_SERIAL_H
+
+#include <platform/hardware.h>
+
+#define BASE_BAUD (*(long *)XTFPGA_CLKFRQ_VADDR / 16)
+
+#endif /* __ASM_XTENSA_XTAVNET_SERIAL_H */
diff --git a/arch/xtensa/platforms/xtfpga/lcd.c b/arch/xtensa/platforms/xtfpga/lcd.c
new file mode 100644 (file)
index 0000000..2872301
--- /dev/null
@@ -0,0 +1,76 @@
+/*
+ * Driver for the LCD display on the Tensilica LX60 Board.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001, 2006 Tensilica Inc.
+ */
+
+/*
+ *
+ * FIXME: this code is from the examples from the LX60 user guide.
+ *
+ * The lcd_pause function does busy waiting, which is probably not
+ * great. Maybe the code could be changed to use kernel timers, or
+ * change the hardware to not need to wait.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <platform/hardware.h>
+#include <platform/lcd.h>
+#include <linux/delay.h>
+
+#define LCD_PAUSE_ITERATIONS   4000
+#define LCD_CLEAR              0x1
+#define LCD_DISPLAY_ON         0xc
+
+/* 8bit and 2 lines display */
+#define LCD_DISPLAY_MODE8BIT   0x38
+#define LCD_DISPLAY_POS                0x80
+#define LCD_SHIFT_LEFT         0x18
+#define LCD_SHIFT_RIGHT                0x1c
+
+static int __init lcd_init(void)
+{
+       *LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT;
+       mdelay(5);
+       *LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT;
+       udelay(200);
+       *LCD_INSTR_ADDR = LCD_DISPLAY_MODE8BIT;
+       udelay(50);
+       *LCD_INSTR_ADDR = LCD_DISPLAY_ON;
+       udelay(50);
+       *LCD_INSTR_ADDR = LCD_CLEAR;
+       mdelay(10);
+       lcd_disp_at_pos("XTENSA LINUX", 0);
+       return 0;
+}
+
+void lcd_disp_at_pos(char *str, unsigned char pos)
+{
+       *LCD_INSTR_ADDR = LCD_DISPLAY_POS | pos;
+       udelay(100);
+       while (*str != 0) {
+               *LCD_DATA_ADDR = *str;
+               udelay(200);
+               str++;
+       }
+}
+
+void lcd_shiftleft(void)
+{
+       *LCD_INSTR_ADDR = LCD_SHIFT_LEFT;
+       udelay(50);
+}
+
+void lcd_shiftright(void)
+{
+       *LCD_INSTR_ADDR = LCD_SHIFT_RIGHT;
+       udelay(50);
+}
+
+arch_initcall(lcd_init);
diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
new file mode 100644 (file)
index 0000000..71d61ca
--- /dev/null
@@ -0,0 +1,269 @@
+/*
+ *
+ * arch/xtensa/platform/xtavnet/setup.c
+ *
+ * ...
+ *
+ * Authors:    Chris Zankel <chris@zankel.net>
+ *             Joe Taylor <joe@tensilica.com>
+ *
+ * Copyright 2001 - 2006 Tensilica Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+
+#include <asm/timex.h>
+#include <asm/processor.h>
+#include <asm/platform.h>
+#include <asm/bootparam.h>
+#include <platform/lcd.h>
+
+void platform_halt(void)
+{
+       lcd_disp_at_pos(" HALT ", 0);
+       local_irq_disable();
+       while (1)
+               cpu_relax();
+}
+
+void platform_power_off(void)
+{
+       lcd_disp_at_pos("POWEROFF", 0);
+       local_irq_disable();
+       while (1)
+               cpu_relax();
+}
+
+void platform_restart(void)
+{
+       /* Flush and reset the mmu, simulate a processor reset, and
+        * jump to the reset vector. */
+
+
+       __asm__ __volatile__ ("movi     a2, 15\n\t"
+                             "wsr      a2, icountlevel\n\t"
+                             "movi     a2, 0\n\t"
+                             "wsr      a2, icount\n\t"
+                             "wsr      a2, ibreakenable\n\t"
+                             "wsr      a2, lcount\n\t"
+                             "movi     a2, 0x1f\n\t"
+                             "wsr      a2, ps\n\t"
+                             "isync\n\t"
+                             "jx       %0\n\t"
+                             :
+                             : "a" (XCHAL_RESET_VECTOR_VADDR)
+                             : "a2"
+                             );
+
+       /* control never gets here */
+}
+
+void __init platform_setup(char **cmdline)
+{
+}
+
+#ifdef CONFIG_OF
+
+static void __init update_clock_frequency(struct device_node *node)
+{
+       struct property *newfreq;
+       u32 freq;
+
+       if (!of_property_read_u32(node, "clock-frequency", &freq) &&
+                       freq != 0)
+               return;
+
+       newfreq = kzalloc(sizeof(*newfreq) + sizeof(u32), GFP_KERNEL);
+       if (!newfreq)
+               return;
+       newfreq->value = newfreq + 1;
+       newfreq->length = sizeof(freq);
+       newfreq->name = kstrdup("clock-frequency", GFP_KERNEL);
+       if (!newfreq->name) {
+               kfree(newfreq);
+               return;
+       }
+
+       *(u32 *)newfreq->value = cpu_to_be32(*(u32 *)XTFPGA_CLKFRQ_VADDR);
+       prom_update_property(node, newfreq);
+}
+
+static int __init machine_setup(void)
+{
+       struct device_node *serial = NULL;
+
+       while ((serial = of_find_compatible_node(serial, NULL, "ns16550a")))
+               update_clock_frequency(serial);
+       return 0;
+}
+arch_initcall(machine_setup);
+
+#endif
+
+/* early initialization */
+
+void __init platform_init(bp_tag_t *first)
+{
+}
+
+/* Heartbeat. */
+
+void platform_heartbeat(void)
+{
+}
+
+#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
+
+void platform_calibrate_ccount(void)
+{
+       long clk_freq = 0;
+#ifdef CONFIG_OF
+       struct device_node *cpu =
+               of_find_compatible_node(NULL, NULL, "xtensa,cpu");
+       if (cpu) {
+               u32 freq;
+               update_clock_frequency(cpu);
+               if (!of_property_read_u32(cpu, "clock-frequency", &freq))
+                       clk_freq = freq;
+       }
+#endif
+       if (!clk_freq)
+               clk_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
+
+       ccount_per_jiffy = clk_freq / HZ;
+       nsec_per_ccount = 1000000000UL / clk_freq;
+}
+
+#endif
+
+#ifndef CONFIG_OF
+
+#include <linux/serial_8250.h>
+#include <linux/if.h>
+#include <net/ethoc.h>
+
+/*----------------------------------------------------------------------------
+ *  Ethernet -- OpenCores Ethernet MAC (ethoc driver)
+ */
+
+static struct resource ethoc_res[] __initdata = {
+       [0] = { /* register space */
+               .start = OETH_REGS_PADDR,
+               .end   = OETH_REGS_PADDR + OETH_REGS_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = { /* buffer space */
+               .start = OETH_SRAMBUFF_PADDR,
+               .end   = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [2] = { /* IRQ number */
+               .start = OETH_IRQ,
+               .end   = OETH_IRQ,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct ethoc_platform_data ethoc_pdata __initdata = {
+       /*
+        * The MAC address for these boards is 00:50:c2:13:6f:xx.
+        * The last byte (here as zero) is read from the DIP switches on the
+        * board.
+        */
+       .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
+       .phy_id = -1,
+};
+
+static struct platform_device ethoc_device __initdata = {
+       .name = "ethoc",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(ethoc_res),
+       .resource = ethoc_res,
+       .dev = {
+               .platform_data = &ethoc_pdata,
+       },
+};
+
+/*----------------------------------------------------------------------------
+ *  UART
+ */
+
+static struct resource serial_resource __initdata = {
+       .start  = DUART16552_PADDR,
+       .end    = DUART16552_PADDR + 0x1f,
+       .flags  = IORESOURCE_MEM,
+};
+
+static struct plat_serial8250_port serial_platform_data[] __initdata = {
+       [0] = {
+               .mapbase        = DUART16552_PADDR,
+               .irq            = DUART16552_INTNUM,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                 UPF_IOREMAP,
+               .iotype         = UPIO_MEM32,
+               .regshift       = 2,
+               .uartclk        = 0,    /* set in xtavnet_init() */
+       },
+       { },
+};
+
+static struct platform_device xtavnet_uart __initdata = {
+       .name           = "serial8250",
+       .id             = PLAT8250_DEV_PLATFORM,
+       .dev            = {
+               .platform_data  = serial_platform_data,
+       },
+       .num_resources  = 1,
+       .resource       = &serial_resource,
+};
+
+/* platform devices */
+static struct platform_device *platform_devices[] __initdata = {
+       &ethoc_device,
+       &xtavnet_uart,
+};
+
+
+static int __init xtavnet_init(void)
+{
+       /* Ethernet MAC address.  */
+       ethoc_pdata.hwaddr[5] = *(u32 *)DIP_SWITCHES_VADDR;
+
+       /* Clock rate varies among FPGA bitstreams; board specific FPGA register
+        * reports the actual clock rate.
+        */
+       serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR;
+
+
+       /* register platform devices */
+       platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+       /* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user
+        * knows whether they set it correctly on the DIP switches.
+        */
+       pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr);
+
+       return 0;
+}
+
+/*
+ * Register to be done during do_initcalls().
+ */
+arch_initcall(xtavnet_init);
+
+#endif /* CONFIG_OF */