tegra: dc: Check DC max pixel clock supported
Pankaj Dabade [Fri, 19 Dec 2014 06:32:40 +0000 (11:32 +0530)]
Check max clock supported by DC before programming it with
that mode. If the requested pixel clock is greater than the
maximum supported then fall back to default mode: 640x480.

Bug 200031813

Change-Id: Icf1f91fe36e29f2c8c6aefe34d3952948743c3a8
Signed-off-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-on: http://git-master/r/666089
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

drivers/video/tegra/dc/dc.c

index 476d045..a1b74a8 100644 (file)
@@ -3171,22 +3171,28 @@ static int tegra_dc_probe(struct platform_device *ndev)
                struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
                if (!tegra_edid_get_monspecs(hdmi->edid, &specs)) {
                        struct tegra_dc_mode *dcmode = &dc->out->modes[0];
-                       dcmode->pclk          = specs.modedb->pixclock;
-                       dcmode->pclk          = PICOS2KHZ(dcmode->pclk);
-                       dcmode->pclk         *= 1000;
-                       dcmode->h_ref_to_sync = 1;
-                       dcmode->v_ref_to_sync = 1;
-                       dcmode->h_sync_width  = specs.modedb->hsync_len;
-                       dcmode->v_sync_width  = specs.modedb->vsync_len;
-                       dcmode->h_back_porch  = specs.modedb->left_margin;
-                       dcmode->v_back_porch  = specs.modedb->upper_margin;
-                       dcmode->h_active      = specs.modedb->xres;
-                       dcmode->v_active      = specs.modedb->yres;
-                       dcmode->h_front_porch = specs.modedb->right_margin;
-                       dcmode->v_front_porch = specs.modedb->lower_margin;
-                       tegra_dc_set_mode(dc, dcmode);
-                       dc->pdata->fb->xres = dcmode->h_active;
-                       dc->pdata->fb->yres = dcmode->v_active;
+                       if (specs.modedb->pixclock >
+                                       tegra_dc_get_out_max_pixclock(dc)) {
+                               dc->mode.pclk = 0;
+                               _tegra_dc_set_default_videomode(dc);
+                       } else {
+                               dcmode->pclk          = specs.modedb->pixclock;
+                               dcmode->pclk          = PICOS2KHZ(dcmode->pclk);
+                               dcmode->pclk         *= 1000;
+                               dcmode->h_ref_to_sync = 1;
+                               dcmode->v_ref_to_sync = 1;
+                               dcmode->h_sync_width  = specs.modedb->hsync_len;
+                               dcmode->v_sync_width  = specs.modedb->vsync_len;
+                               dcmode->h_back_porch  = specs.modedb->left_margin;
+                               dcmode->v_back_porch  = specs.modedb->upper_margin;
+                               dcmode->h_active      = specs.modedb->xres;
+                               dcmode->v_active      = specs.modedb->yres;
+                               dcmode->h_front_porch = specs.modedb->right_margin;
+                               dcmode->v_front_porch = specs.modedb->lower_margin;
+                               tegra_dc_set_mode(dc, dcmode);
+                               dc->pdata->fb->xres = dcmode->h_active;
+                               dc->pdata->fb->yres = dcmode->v_active;
+                       }
                }
        }
 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */