ARM: tegra: Rename flow control registers
Scott Williams [Thu, 21 Jul 2011 20:32:21 +0000 (13:32 -0700)]
Change-Id: I2647718dc9c9420e57b24a810738c33ef05bcf61
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R6d5c6a52a2b0fd1dafd021d4a187528aeca26516

arch/arm/mach-tegra/sleep-t20.S
arch/arm/mach-tegra/sleep.h

index f7f119c..13fc1dc 100644 (file)
@@ -406,8 +406,8 @@ tegra2_enter_sleep:
        dsb
        mov32   r6, TEGRA_FLOW_CTRL_BASE
 
-       mov     r0, #FLOW_CTRL_STOP_UNTIL_IRQ
-       orr     r0, r0, #FLOW_CTRL_IRQ_RESUME | FLOW_CTRL_FIQ_RESUME
+       mov     r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
+       orr     r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
        cpu_id  r1
        cpu_to_halt_reg r1, r1
        str     r0, [r6, r1]
index a36b98e..dbbe7a3 100644 (file)
 #define CPU_RESETTABLE_SOON            1
 #define CPU_NOT_RESETTABLE             0
 
-#define FLOW_CTRL_WAITEVENT            (2 << 29)
-#define FLOW_CTRL_STOP_UNTIL_IRQ       (4 << 29)
-#define FLOW_CTRL_JTAG_RESUME          (1 << 28)
-#define FLOW_CTRL_IRQ_RESUME           (1 << 10)
-#define FLOW_CTRL_FIQ_RESUME           (1 << 8)
-
-#define FLOW_CTRL_CSR_INTR_FLAG                (1<<15)
-#define FLOW_CTRL_CSR_EVENT_FLAG       (1<<14)
-
 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
                                        + IO_CPU_VIRT)
 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \