ARM: tegra: power: Do not switch Tegra3 to PLLP
Alex Frid [Sat, 1 Oct 2011 01:38:59 +0000 (18:38 -0700)]
Do not switch Tegra3 to PLLP on sleep entry: no need - unlike Tegra2
PLLX on Tegra3 is not disabled when CPU is rail gated; also G/LP mode
switch clock configuration is set by mode switch prolog and should not
be overwritten at the last moment.

Change-Id: I9aa8463c6b1c04c0a70e70c1e2cd4113a679e100
Reviewed-on: http://git-master/r/57202
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R9a8d78a363c261d45e48832fcbed7fa2854f7da8

arch/arm/mach-tegra/sleep-t30.S

index abb4aa6..a30dabf 100644 (file)
@@ -90,6 +90,7 @@
 #define MSELECT_CLKM                   (0x3 << 30)
 
 #define USE_PLL_LOCK_BITS 0
+#define USE_PLLP_ON_SLEEP_ENTRY 0
 
 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
 
@@ -246,8 +247,9 @@ ENTRY(tegra3_tear_down_cpu)
        mov32   r5, TEGRA_CLK_RESET_BASE
        mov32   r6, TEGRA_FLOW_CTRL_BASE
        mov32   r7, TEGRA_TMRUS_BASE
-
+#if USE_PLLP_ON_SLEEP_ENTRY
        bl      tegra_cpu_pllp
+#endif
        b       tegra3_enter_sleep
 ENDPROC(tegra3_tear_down_cpu)