tegra: dc: Unsetting DC to default mode in probe
Pankaj Dabade [Tue, 20 Jan 2015 06:36:15 +0000 (11:36 +0530)]
During probe, for L4t-HDMI, monitor specs are read and set
before DC is enabled. DC will fall back to default mode
only when a invalid request is made by monitor.

Bug 200020671
Bug 200031813

Change-Id: I5138e76afe8b2e5bfef1ee1941455827df34a1c0
Signed-off-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-on: http://git-master/r/673655
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

drivers/video/tegra/dc/dc.c

index 986fabe..ee63249 100644 (file)
@@ -3171,28 +3171,29 @@ static int tegra_dc_probe(struct platform_device *ndev)
                struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
                if (!tegra_edid_get_monspecs(hdmi->edid, &specs)) {
                        struct tegra_dc_mode *dcmode = &dc->out->modes[0];
-                       if (specs.modedb->pixclock >
-                                       tegra_dc_get_out_max_pixclock(dc)) {
-                               dc->mode.pclk = 0;
-                               _tegra_dc_set_default_videomode(dc);
-                       } else {
-                               dcmode->pclk          = specs.modedb->pixclock;
-                               dcmode->pclk          = PICOS2KHZ(dcmode->pclk);
-                               dcmode->pclk         *= 1000;
-                               dcmode->h_ref_to_sync = 1;
-                               dcmode->v_ref_to_sync = 1;
-                               dcmode->h_sync_width  = specs.modedb->hsync_len;
-                               dcmode->v_sync_width  = specs.modedb->vsync_len;
-                               dcmode->h_back_porch  = specs.modedb->left_margin;
-                               dcmode->v_back_porch  = specs.modedb->upper_margin;
-                               dcmode->h_active      = specs.modedb->xres;
-                               dcmode->v_active      = specs.modedb->yres;
-                               dcmode->h_front_porch = specs.modedb->right_margin;
-                               dcmode->v_front_porch = specs.modedb->lower_margin;
+                       dcmode->pclk          = specs.modedb->pixclock;
+                       dcmode->pclk          = PICOS2KHZ(dcmode->pclk);
+                       dcmode->pclk         *= 1000;
+                       dcmode->h_ref_to_sync = 1;
+                       dcmode->v_ref_to_sync = 1;
+                       dcmode->h_sync_width  = specs.modedb->hsync_len;
+                       dcmode->v_sync_width  = specs.modedb->vsync_len;
+                       dcmode->h_back_porch  = specs.modedb->left_margin;
+                       dcmode->v_back_porch  = specs.modedb->upper_margin;
+                       dcmode->h_active      = specs.modedb->xres;
+                       dcmode->v_active      = specs.modedb->yres;
+                       dcmode->h_front_porch = specs.modedb->right_margin;
+                       dcmode->v_front_porch = specs.modedb->lower_margin;
+
+                       /* Program DC only with supported pclk. If pclk is not
+                        * supported, fall back to default mode.
+                        */
+                       if (dcmode->pclk > PICOS2KHZ(tegra_dc_get_out_max_pixclock(dc)) * 1000)
+                               tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
+                       else
                                tegra_dc_set_mode(dc, dcmode);
-                               dc->pdata->fb->xres = dcmode->h_active;
-                               dc->pdata->fb->yres = dcmode->v_active;
-                       }
+                       dc->pdata->fb->xres = dcmode->h_active;
+                       dc->pdata->fb->yres = dcmode->v_active;
                }
        }
 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
@@ -3248,6 +3249,8 @@ static int tegra_dc_probe(struct platform_device *ndev)
                        udelay(10);
                        clk_disable_unprepare(dc->clk);
                }
+               if (dc->out->type != TEGRA_DC_OUT_HDMI)
+                       _tegra_dc_set_default_videomode(dc);
                dc->enabled = _tegra_dc_enable(dc);
 
 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)