ARM: Tegra: Fix PowerGate status logic
Bhavesh Parekh [Thu, 31 Oct 2013 06:45:22 +0000 (11:45 +0530)]
In the code we are reading value of PMC_PWRGATE_TOGGLE in reg variable.
But loop was checking for status variable. Fix the same

Change-Id: If18bf9ddcb403b60f084dee2edf3980e06ff2e3b
Signed-off-by: Bhavesh Parekh <bparekh@nvidia.com>
Reviewed-on: http://git-master/r/309991
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

arch/arm/mach-tegra/powergate.c

index 5f45c3a..a8fc894 100644 (file)
@@ -95,7 +95,7 @@ int tegra_powergate_set(int id, bool new_state)
                udelay(1);
                reg = pmc_read(PWRGATE_TOGGLE);
                contention_timeout--;
-       } while ((contention_timeout > 0) && (status & PWRGATE_TOGGLE_START));
+       } while ((contention_timeout > 0) && (reg & PWRGATE_TOGGLE_START));
 
        if (contention_timeout <= 0)
                pr_err(" Timed out waiting for PMC to submit \
@@ -112,7 +112,7 @@ int tegra_powergate_set(int id, bool new_state)
                udelay(1);
                reg = pmc_read(PWRGATE_TOGGLE);
                contention_timeout--;
-       } while ((contention_timeout > 0) && (status & PWRGATE_TOGGLE_START));
+       } while ((contention_timeout > 0) && (reg & PWRGATE_TOGGLE_START));
 
        if (contention_timeout <= 0)
                pr_err(" Timed out waiting for PMC to accept \