ARM: tegra11: clock: Rearrange XUSB clocks for 11x and 12x
Ajay Gupta [Thu, 6 Jun 2013 23:02:44 +0000 (16:02 -0700)]
We need different HS clock sources in 11x for HS disconnect
SW WAR. The clock source table is incorrect for 11x and 12x
so fixing same.

Change-Id: I87d13534b5a573b62ee06d5cbf10774ff899d426
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242026
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

arch/arm/mach-tegra/common.c

index 8c8dac9..7a03db8 100644 (file)
@@ -300,8 +300,8 @@ static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
        { "pll_re_vco", NULL,           612000000,      false },
        { "xusb_falcon_src",    "pll_p",        204000000,      false},
        { "xusb_host_src",      "pll_p",        102000000,      false},
-       { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
-       { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
+       { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
+       { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
        { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
        { "sdmmc1",     "pll_p",        48000000,       false},
        { "sdmmc3",     "pll_p",        48000000,       false},
@@ -384,11 +384,11 @@ static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
        { "csite",      NULL,           0,              true },
 #endif
        { "pll_u",      NULL,           480000000,      true },
-       { "pll_re_vco", NULL,           612000000,      true },
-       { "xusb_falcon_src",    "pll_p",        204000000,      false},
-       { "xusb_host_src",      "pll_p",        102000000,      false},
-       { "xusb_ss_src",        "pll_re_vco",   122400000,      false},
-       { "xusb_hs_src",        "xusb_ss_div2", 61200000,       false},
+       { "pll_re_vco", NULL,           672000000,      false },
+       { "xusb_falcon_src",    "pll_re_vco",   224000000,      false},
+       { "xusb_host_src",      "pll_re_vco",   112000000,      false},
+       { "xusb_ss_src",        "pll_u_480M",   120000000,      false},
+       { "xusb_hs_src",        "pll_u_60M",    60000000,       false},
        { "xusb_fs_src",        "pll_u_48M",    48000000,       false},
        { "sdmmc1",     "pll_p",        48000000,       false},
        { "sdmmc3",     "pll_p",        48000000,       false},