ARM: tegra11: clock: Fix boot over-clocking warnings
Alex Frid [Sun, 17 Feb 2013 08:39:45 +0000 (00:39 -0800)]
- Increase maximum rate for secondary PLLM output to the main PLLM
output limit
- Removed non supported sata clocks from the clock tree

Change-Id: I208df494a41ed620937086feb0271cd1dc85a5b6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/201537
(cherry picked from commit c70f6b86b9f46226cc8fed5fa76ef1e05d315dd8)
Reviewed-on: http://git-master/r/203618
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 60256dd..dbd10b8 100644 (file)
@@ -5432,7 +5432,7 @@ static struct clk tegra_pll_m_out1 = {
        .parent    = &tegra_pll_m,
        .reg       = 0x94,
        .reg_shift = 0,
-       .max_rate  = 600000000,
+       .max_rate  = 1066000000,
 };
 
 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
@@ -6521,9 +6521,6 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("sbc4",      "spi-tegra114.3",       NULL,   68,     0x1b4,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sbc5",      "spi-tegra114.4",       NULL,   104,    0x3c8,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("sbc6",      "spi-tegra114.5",       NULL,   105,    0x3cc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-       PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   PERIPH_ON_APB),
        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB,  &tegra_nand_clk_ops),
        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),