ARM: tegra: disable SDIO clock gating
R Raj Kumar [Mon, 23 Sep 2013 08:52:09 +0000 (13:52 +0530)]
SD/SDIO/EMMC Clock gate control done through
board platform data. SDIO clock gate disabled
for all boards.

Bug 1360926
Bug 1299485

Change-Id: I64bd530a1fcb862bc67b363b7ab5537f995a3fd3
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/304724
Reviewed-by: Automatic_Commit_Validation_User

arch/arm/mach-tegra/board-ardbeg-sdhci.c
arch/arm/mach-tegra/board-bonaire-sdhci.c
arch/arm/mach-tegra/board-dalmore-sdhci.c
arch/arm/mach-tegra/board-loki-sdhci.c
arch/arm/mach-tegra/board-macallan-sdhci.c
arch/arm/mach-tegra/board-pismo-sdhci.c
arch/arm/mach-tegra/board-pluto-sdhci.c
arch/arm/mach-tegra/board-roth-sdhci.c
arch/arm/mach-tegra/board-vcm30_t124-sdhci.c

index bea9e42..2b0e230 100644 (file)
@@ -184,6 +184,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
                MMC_UHS_MASK_SDR50,
        .calib_3v3_offsets = 0x7676,
        .calib_1v8_offsets = 0x7676,
+       .disable_clock_gate = true,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
index f08568b..88d3c2d 100644 (file)
@@ -91,6 +91,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .cd_gpio = -1,
        .wp_gpio = -1,
        .power_gpio = -1,
+       .disable_clock_gate = true,
 /*     .max_clk = 12000000, */
 };
 
index cbd1587..1019fa4 100644 (file)
@@ -114,6 +114,7 @@ struct tegra_sdhci_platform_data dalmore_tegra_sdhci_platform_data0 = {
 /*FIXME: Enable UHS modes for WiFI */
        .uhs_mask = MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50 |
                MMC_UHS_MASK_SDR104 | MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25,
+       .disable_clock_gate = true,
 };
 
 static struct resource sdhci_resource0[] = {
index b0306b2..8483350 100644 (file)
@@ -156,6 +156,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
                MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50,
        .calib_3v3_offsets = 0x7676,
        .calib_1v8_offsets = 0x7676,
+       .disable_clock_gate = true,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
index 477cee8..732b470 100644 (file)
@@ -91,6 +91,7 @@ struct tegra_sdhci_platform_data macallan_tegra_sdhci_platform_data0 = {
        .trim_delay = 0x2,
        .ddr_clk_limit = 41000000,
        .uhs_mask = MMC_UHS_MASK_DDR50,
+       .disable_clock_gate = true,
 };
 
 #ifndef CONFIG_USE_OF
index 92cdd6d..ecabfd6 100644 (file)
@@ -2,7 +2,7 @@
  * arch/arm/mach-tegra/board-pismo-sdhci.c
  *
  * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2012 NVIDIA Corporation.
+ * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  *
  */
-
 #include <linux/resource.h>
 #include <linux/platform_device.h>
 #include <linux/wlan_plat.h>
@@ -149,6 +148,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .ddr_clk_limit = 41000000,
        .uhs_mask = MMC_UHS_MASK_SDR104 |
                MMC_UHS_MASK_DDR50,
+       .disable_clock_gate = true,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
index 2c6c2da..fb42b58 100644 (file)
@@ -117,6 +117,7 @@ struct tegra_sdhci_platform_data pluto_tegra_sdhci_platform_data0 = {
        .ddr_clk_limit = 41000000,
        .max_clk_limit = 82000000,
        .uhs_mask = MMC_UHS_MASK_DDR50,
+       .disable_clock_gate = true,
 };
 
 static struct resource sdhci_resource0[] = {
index 5b1bc67..0d334ff 100644 (file)
@@ -152,6 +152,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .trim_delay = 0x2,
        .ddr_clk_limit = 41000000,
        .uhs_mask = MMC_UHS_MASK_DDR50,
+       .disable_clock_gate = true,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
index b77602f..c2d8367 100644 (file)
@@ -95,6 +95,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data1 = {
        .tap_delay = 0x0F,
        .ddr_clk_limit = 30000000,
        .is_8bit = false,
+       .disable_clock_gate = true,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {