ARM: tegra: Clean up flow controller CSR macros
Bo Yan [Sat, 19 May 2012 02:55:18 +0000 (19:55 -0700)]
Group flow controller macros for CSR register in one place in sleep.h
Also strip "CPU" out of macro names because the corresponding COP CSR
register has only one field INTR_FLAG which is at bit 15, same as CPU
CSR, so there is no confusion here.

Change-Id: Ib3dea0bd3e9051d1e7b9048abc4afde5ddc8bab5
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103478
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>

Rebase-Id: R63c198f17e573818b8d44482c46cb61516bf1267

arch/arm/mach-tegra/cpuidle.c
arch/arm/mach-tegra/pm-t3.c
arch/arm/mach-tegra/pm.h
arch/arm/mach-tegra/sleep.h

index 54af4df..f6b568e 100644 (file)
@@ -160,7 +160,7 @@ static int tegra_idle_enter_lp2(struct cpuidle_device *dev,
 #define        POWER_GATING_OPTION_LEN 8
 static char power_gating_option[8] __read_mostly =
                                                                                        {'c', 'r', 'a', 'i', 'l', '\0'};
-static int power_gating_mode = FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL;
+static int power_gating_mode = FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
 static struct kparam_string power_gating __read_mostly = {
        .maxlen = POWER_GATING_OPTION_LEN,
        .string = power_gating_option,
@@ -178,11 +178,11 @@ static int power_gating_set(const char *buffer, const struct kernel_param *kp)
        }
 
        if (!strncmp(buffer, "noncpu", 6))
-               mode = FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU;
+               mode = FLOW_CTRL_CSR_ENABLE_EXT_NCPU;
        else if (!strncmp(buffer, "crail", 5))
-               mode = FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL;
+               mode = FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
        else if (!strncmp(buffer, "emu", 3))
-               mode = FLOW_CTRL_CPU_CSR_ENABLE_EXT_MASK;
+               mode = FLOW_CTRL_CSR_ENABLE_EXT_MASK;
        else if (!strncmp(buffer, "cpu", 3))
                mode = 0;
 
index 700ab96..e6a9945 100644 (file)
@@ -200,23 +200,23 @@ void tegra_cluster_switch_prolog(unsigned int flags)
           and immediate flags. If an actual CPU switch is to be performed,
           re-write the CSR register with the desired values. */
        reg = readl(FLOW_CTRL_CPU_CSR(0));
-       reg &= ~(FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE |
-                FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER);
+       reg &= ~(FLOW_CTRL_CSR_IMMEDIATE_WAKE |
+                FLOW_CTRL_CSR_SWITCH_CLUSTER);
 
        /* Program flow controller for immediate wake if requested */
        if (flags & TEGRA_POWER_CLUSTER_IMMEDIATE)
-               reg |= FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE;
+               reg |= FLOW_CTRL_CSR_IMMEDIATE_WAKE;
 
        /* Do nothing if no switch actions requested */
        if (!target_cluster)
                goto done;
 
 #if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE)
-       reg &= ~FLOW_CTRL_CPU_CSR_ENABLE_EXT_MASK;
+       reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
        if (flags & TEGRA_POWER_CLUSTER_PART_CRAIL)
-               reg |= FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL;
+               reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
        if (flags & TEGRA_POWER_CLUSTER_PART_NONCPU)
-               reg |= FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU;
+               reg |= FLOW_CTRL_CSR_ENABLE_EXT_NCPU;
 #endif
 
        if ((current_cluster != target_cluster) ||
@@ -229,7 +229,7 @@ void tegra_cluster_switch_prolog(unsigned int flags)
                        }
 
                        /* Set up the flow controller to switch CPUs. */
-                       reg |= FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER;
+                       reg |= FLOW_CTRL_CSR_SWITCH_CLUSTER;
                }
        }
 
@@ -302,10 +302,10 @@ void tegra_cluster_switch_epilog(unsigned int flags)
           the flow controller to prevent undesirable side-effects
           for future users of the flow controller. */
        reg = readl(FLOW_CTRL_CPU_CSR(0));
-       reg &= ~(FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE |
-                FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER);
+       reg &= ~(FLOW_CTRL_CSR_IMMEDIATE_WAKE |
+                FLOW_CTRL_CSR_SWITCH_CLUSTER);
 #if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE)
-       reg &= ~FLOW_CTRL_CPU_CSR_ENABLE_EXT_MASK;
+       reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
 #endif
        writel(reg, FLOW_CTRL_CPU_CSR(0));
 
index a5b7ce7..a40d384 100644 (file)
@@ -84,13 +84,6 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags);
 
 #define FLOW_CTRL_CLUSTER_CONTROL \
        (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x2c)
-#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL     (1<<13)
-#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU      (1<<12)
-#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_MASK      ( \
-       FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU | \
-       FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL )
-#define FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE       (1<<3)
-#define FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER       (1<<2)
 
 #define FLOW_CTRL_CPU_PWR_CSR \
        (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x38)
index ee6cd3a..83a5d64 100644 (file)
 #define   FLOW_CTRL_HALT_GIC_FIQ       (1 << 8)
 #define   FLOW_CTRL_IMMEDIATE_WAKE     (1 << 3)
 #define FLOW_CTRL_CPU0_CSR             0x8
-#define   FLOW_CTRL_CSR_INTR_FLAG      (1 << 15)
-#define   FLOW_CTRL_CSR_EVENT_FLAG     (1 << 14)
-#define   FLOW_CTRL_CSR_ENABLE         (1 << 0)
+#define   FLOW_CTRL_CSR_INTR_FLAG              (1 << 15)
+#define   FLOW_CTRL_CSR_EVENT_FLAG             (1 << 14)
+#define   FLOW_CTRL_CSR_ENABLE_EXT_NONE        (0)
+#define   FLOW_CTRL_CSR_ENABLE_EXT_CRAIL       (1<<13)
+#define   FLOW_CTRL_CSR_ENABLE_EXT_NCPU        (1<<12)
+#define   FLOW_CTRL_CSR_ENABLE_EXT_MASK        ( \
+                                       FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
+                                       FLOW_CTRL_CSR_ENABLE_EXT_CRAIL )
+#define   FLOW_CTRL_CSR_ENABLE_EXT_EMU FLOW_CTRL_CSR_ENABLE_EXT_MASK
+#define   FLOW_CTRL_CSR_IMMEDIATE_WAKE         (1<<3)
+#define   FLOW_CTRL_CSR_SWITCH_CLUSTER         (1<<2)
+#define   FLOW_CTRL_CSR_ENABLE                 (1 << 0)
+
 #define FLOW_CTRL_HALT_CPU1_EVENTS     0x14
 #define FLOW_CTRL_CPU1_CSR             0x18