video: tegra: host: Lower initial GPU rate
Alex Frid [Tue, 5 Nov 2013 05:06:30 +0000 (21:06 -0800)]
Set initial GPCPLL rate to 504MHz - half of minimum VCO rate.
Respectively initialize GPU bus rate to half of GPCPLL rate - 252MHz
(was - maximum GPU rate supported).

These changes made sure that initial GPU voltage is low enough for
tegra SiMon to evaluate GPU state on boot even on the slowest part.

Bug 1343366

Change-Id: I972ea504e36550a304c4c70d9c5d56f3c00286cb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/326389
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/common.c
drivers/video/tegra/host/gk20a/clk_gk20a.c

index a58b591..15dedca 100644 (file)
@@ -458,6 +458,7 @@ static __initdata struct tegra_clk_init_table tegra12x_clk_init_table[] = {
        { "sbc6.sclk",  NULL,           40000000,       false},
        { "cpu.mselect", NULL,          102000000,      true},
        { "gpu_ref",    NULL,           0,              true},
+       { "gk20a.gbus", NULL,           252000000,      false},
 #ifdef CONFIG_TEGRA_PLLM_SCALED
        { "vi",         "pll_p",        0,              false},
        { "isp",        "pll_p",        0,              false},
index 6295122..10fadcd 100644 (file)
@@ -474,8 +474,9 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g)
                clk->gpc_pll.M = 1;
                clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco,
                                        clk->gpc_pll.clk_in);
-               clk->gpc_pll.PL = 0;
+               clk->gpc_pll.PL = 1;
                clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N;
+               clk->gpc_pll.freq /= pl_to_div[clk->gpc_pll.PL];
        }
 
        err = tegra_dvfs_get_freqs(clk_get_parent(clk->tegra_clk),