ARM: tegra11x: Define ncpu residency for 2 clusters
Bo Yan [Tue, 5 Feb 2013 17:57:10 +0000 (09:57 -0800)]
There is no compelling reason to define minimum residency of non CPU
power gating for each different platform. Non CPU power gating has
far less dependency on platform in terms of latency when compared
against rail gating. So move this parameter to CPU specific idle
driver code.

Define minimum residency of non CPU power gating for both slow and
fast cluster. The entry criteria is different for two clusters, so
different value are required.

Change-Id: I3f734d056f6de6a804ca4c14e037a98bc07c646d
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/197537
Reviewed-on: http://git-master/r/200856
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

arch/arm/mach-tegra/board-dalmore-power.c
arch/arm/mach-tegra/board-pluto-power.c
arch/arm/mach-tegra/board-roth-power.c
arch/arm/mach-tegra/cpuidle-t11x.c
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/pm.h

index 47c4521..fe6084a 100644 (file)
@@ -993,8 +993,7 @@ static struct tegra_suspend_platform_data dalmore_suspend_data = {
        .corereq_high   = true,
        .sysclkreq_high = true,
        .cpu_lp2_min_residency = 1000,
-       .min_residency_noncpu = 2000,
-       .min_residency_crail = 8000,
+       .min_residency_crail = 20000,
 };
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 /* board parameters for cpu dfll */
index a5a69c4..9c23b55 100644 (file)
@@ -688,8 +688,7 @@ static struct tegra_suspend_platform_data pluto_suspend_data = {
        .corereq_high   = true,
        .sysclkreq_high = true,
        .cpu_lp2_min_residency = 1000,
-       .min_residency_noncpu = 2000,
-       .min_residency_crail = 8000,
+       .min_residency_crail = 20000,
 };
 
 int __init pluto_suspend_init(void)
index 1cb3bc4..da20c66 100644 (file)
@@ -592,8 +592,7 @@ static struct tegra_suspend_platform_data roth_suspend_data = {
        .corereq_high   = true,
        .sysclkreq_high = true,
        .cpu_lp2_min_residency = 1000,
-       .min_residency_noncpu = 2000,
-       .min_residency_crail = 8000,
+       .min_residency_crail = 20000,
 };
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 /* board parameters for cpu dfll */
index 00cf3e0..4d8b496 100644 (file)
@@ -72,6 +72,9 @@
 #define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
 #define ARCH_TIMER_CTRL_IT_MASK         (1 << 1)
 
+#define TEGRA_MIN_RESIDENCY_NCPU_SLOW 2000
+#define TEGRA_MIN_RESIDENCY_NCPU_FAST 13000
+
 #ifdef CONFIG_SMP
 static s64 tegra_cpu_wake_by_time[4] = {
        LLONG_MAX, LLONG_MAX, LLONG_MAX, LLONG_MAX };
@@ -472,7 +475,7 @@ bool tegra11x_idle_power_down(struct cpuidle_device *dev,
 
        if (is_lp_cluster()) {
                if (slow_cluster_power_gating_noncpu &&
-                       (request > tegra_min_residency_noncpu()))
+                       (request > TEGRA_MIN_RESIDENCY_NCPU_SLOW))
                                power_gating_cpu_only = false;
                else
                        power_gating_cpu_only = true;
@@ -482,7 +485,7 @@ bool tegra11x_idle_power_down(struct cpuidle_device *dev,
                if (fast_cluster_power_down_mode &&
                        TEGRA_POWER_CLUSTER_FORCE_MASK)
                        power_gating_cpu_only = cpu_gating_only;
-               else if (request > tegra_min_residency_noncpu())
+               else if (request > TEGRA_MIN_RESIDENCY_NCPU_FAST)
                        power_gating_cpu_only = false;
                else
                        power_gating_cpu_only = true;
index 63973a5..a63471d 100644 (file)
@@ -257,11 +257,6 @@ unsigned long tegra_cpu_lp2_min_residency(void)
 }
 
 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
-unsigned long tegra_min_residency_noncpu(void)
-{
-       return pdata->min_residency_noncpu;
-}
-
 unsigned long tegra_min_residency_crail(void)
 {
        return pdata->min_residency_crail;
index fafcf96..94ff396 100644 (file)
@@ -74,7 +74,6 @@ struct tegra_suspend_platform_data {
        unsigned int lp1_core_volt_high;
 #endif
 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
-       unsigned long min_residency_noncpu;
        unsigned long min_residency_crail;
 #endif
 };
@@ -86,7 +85,6 @@ unsigned long tegra_cpu_power_good_time(void);
 unsigned long tegra_cpu_power_off_time(void);
 unsigned long tegra_cpu_lp2_min_residency(void);
 #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
-unsigned long tegra_min_residency_noncpu(void);
 unsigned long tegra_min_residency_crail(void);
 #endif
 void tegra_clear_cpu_in_pd(int cpu);