ARM: tegra: sdhci: set max clk to 200MHz for SDMMC3
authorShreshtha Sahu <ssahu@nvidia.com>
Wed, 21 May 2014 06:39:50 +0000 (11:39 +0530)
committerWinnie Hsu <whsu@nvidia.com>
Wed, 21 May 2014 21:54:22 +0000 (14:54 -0700)
commitfbcb0018d3622dedeb4c9413b9b774c4c9d49d36
tree6f3a1363ab3498df7aa8911d6caa1010fb0ebd4f
parent3fef90e08330c9ed11f84adf8f98492d3b917ddb
ARM: tegra: sdhci: set max clk to 200MHz for SDMMC3

This patch sets max clk limit to 200MHz for SDMMC3 for PM375.
Requesting 208MHz results in getting 204MHz from PLL_P and CRC
errors are seen.

Bug 1505798

Change-Id: I14825335fa5895ef2dde905f1e3cd568d2dafa62
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/412542
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
arch/arm/mach-tegra/board-ardbeg-sdhci.c