arm: tegra3: PCIe PLL Reset
authorEric Yuen <eyuen@nvidia.com>
Sat, 22 Jun 2013 22:00:21 +0000 (15:00 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:28:21 +0000 (13:28 -0700)
commitfa5f5d71bfe64b2d4c13882fba40aa2c515237d2
treed8f837a5cc49b1b034e5e3bb8b990fc67d9ce53e
parent5b29eb563700bf1cfedb6a224a33242511f53ace
arm: tegra3: PCIe PLL Reset

Workaround of PLL Setup.

Bug 1302133
Bug 1313433

Change-Id: I718e8a355cd0e8c86c1930c5fd036cb06e9f6f89
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Reviewed-on: http://git-master/r/241227
(cherry picked from commit 86b877e7604e28c6c4621048ac9c0f6943dd7221)
Signed-off-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-on: http://git-master/r/245007
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Ashutosh Patel <ashutoshp@nvidia.com>
arch/arm/mach-tegra/pcie.c