ARM: tegra: power: Re-factor Tegra3 secondary CPU LP2 entry
authorAlex Frid <afrid@nvidia.com>
Sun, 29 Jan 2012 01:36:37 +0000 (17:36 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 07:59:13 +0000 (00:59 -0700)
commitfa13e447e371c01d04d66d6da299604985072352
tree0a399aef147637fb6ca042ee058e8dd42940d4b4
parent84b7ea8a6c77c3e7adab0ee5c7b21d1025f06c13
ARM: tegra: power: Re-factor Tegra3 secondary CPU LP2 entry

When Tegra3 secondary CPU is entering LP2, read TWD timer state
into context structure, rather than separate local variables.

Reviewed-on: http://git-master/r/77957

Change-Id: I237eafc50a11d535b94f334631d039ba9c4bf44b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78899
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Ra2fb8f72f23c8aac06757aba504623ea45ae4185
arch/arm/mach-tegra/cpuidle-t3.c
arch/arm/mach-tegra/timer.c
arch/arm/mach-tegra/timer.h