ARM: tegra11: dvfs: Re-arrange DFLL clock initialization
authorAlex Frid <afrid@nvidia.com>
Wed, 27 Feb 2013 22:59:31 +0000 (14:59 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:04:07 +0000 (13:04 -0700)
commitf9ce22b8881f4aeba4366d39a8d21dcc9eb71301
tree5e52f8c17a3781ce9fec05a58008228d71b72151
parent99d2974ef1758f92afb4ade47cb39881cb7b8bfd
ARM: tegra11: dvfs: Re-arrange DFLL clock initialization

- Re-assigned DFLL clock init operation to late init function inside
init operation itslef (instead of external assignment during global
tegra11x clocks initialization)

- Included into DFLL clock initialization call to Cl-DVFS debug init,
so that DFLL clock pointer can be passed as an argument, rather than
retrieved in CL-DVFS debug init from hard coded DFLL clock name.

- Added write attribute to tune_high_mv debugfs entry

Change-Id: I03c4cd5e33d7f27ad73ae3319ee1c318e135a639
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/204969
Reviewed-on: http://git-master/r/210461
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra14_clocks.c
arch/arm/mach-tegra/tegra_cl_dvfs.c
arch/arm/mach-tegra/tegra_cl_dvfs.h