ARM: tegra11: clock: Support non-linear pll post dividers
authorAlex Frid <afrid@nvidia.com>
Fri, 25 May 2012 06:16:09 +0000 (23:16 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:11:36 +0000 (12:11 -0700)
commiteef314c99e03493041055d6bbe378d559028ad50
tree9ab589c3edac0e74e99e9e2623af603497f48351
parent8c50ed719ef5698e474b17d500002731053f729e
ARM: tegra11: clock: Support non-linear pll post dividers

Added non-linear look-up table to map PLLC2/PLLC3 post dividers
settings into divisor values, and re-factor pll set rate operation
accordingly. Apply similar re-factoring to PLLX/PLLC, although
divider settings for these plls are still limited by s/w to the
range with linear mapping.

Change-Id: I8f968f6d243d974836c98b05dd9425aa5eab7280
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106077
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb559949ec22722e30ec3ead3ed98fbba4736598b
arch/arm/mach-tegra/clock.h
arch/arm/mach-tegra/tegra11_clocks.c