ARM: tegra11: clock: Fix SCLK input mux
authorAlex Frid <afrid@nvidia.com>
Thu, 17 Jan 2013 02:40:11 +0000 (18:40 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:50:34 +0000 (12:50 -0700)
commited97e50f4ce37efa14981be9a68a5f07a73f4c81
treecb2ce9b1a41c22cebe78106b872b28dc9a1a828c
parent3cbced756e96ca15dc563ce4facc931d48602eb8
ARM: tegra11: clock: Fix SCLK input mux

Replaced secondary divider PLLP_OUT3 in system clock input mux
definition with main PLLP output to match h/w.

Change-Id: Icdf2de2bf79665bccbe9e68d12386e0b9738960f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191893
(cherry picked from commit c26c8139a29d4fc892deb5c4487486b43e7fac1f)
Reviewed-on: http://git-master/r/192656
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
arch/arm/mach-tegra/tegra11_clocks.c