ARM: tegra: clock: Update CPU cluster switch clock control
authorAlex Frid <afrid@nvidia.com>
Wed, 13 Feb 2013 23:55:56 +0000 (15:55 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:02:15 +0000 (13:02 -0700)
commitdf9615101d0b28af17a2b7be1b876babf8707baf
tree420c2cd9eb870a9c632e87bc438aa9f287475954
parent5cd2f04484dea65a5ea806d27daf2ae123cc1eae
ARM: tegra: clock: Update CPU cluster switch clock control

Updated clock control when cluster round trip changes CPU clock
source from PLL to DFLL: G CPU (PLL) => LP CPU (PLL) => G CPU (DFLL).

- made sure that PLL used as G CPU clock source during the last
residency is enabled across LP-to-G switch
- made sure that initial G CPU voltage is preset before cluster
switch to maximum of voltage levels required for G CPU running on
last residency PLL and next residency DFLL
- changed G CPU rail control from s/w dvfs to h/w cl-dvfs after the
switch to G CPU is completed

Change-Id: I7720cda544ef16a4691534b52315e9128b2b27c3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/201830
(cherry picked from commit fd9b858e4443860b3538f8e85eacdb24bf32c59b)
Reviewed-on: http://git-master/r/207894
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>
arch/arm/mach-tegra/dvfs.h
arch/arm/mach-tegra/tegra11_clocks.c