mmc: tegra: Fix parent clk configuration
authorPavan Kunapuli <pkunapuli@nvidia.com>
Fri, 28 Mar 2014 11:43:24 +0000 (16:43 +0530)
committerWinnie Hsu <whsu@nvidia.com>
Wed, 21 May 2014 22:00:16 +0000 (15:00 -0700)
commitddf408b5b5d3018bc583a8b51ead3ff19e7a7bc5
tree4b10f985394d226c0a4594f7c7077a9d709d01b6
parentf2a9fc57238de62bc996f7565850b7012e1f5962
mmc: tegra: Fix parent clk configuration

Do not ignore parent clk setting and parent clock source flag
update for any case. For eMMC, in resume, without pll_c as clk
source, 200MHz cannot be set in HS200 mode set.

Bug 1480583

Reviewed-on: http://git-master/r/389704
(cherry picked from commit b9b0cb1541d66ba2450a680666c3fe962b4f71df)

Change-Id: I7898a57871cd16de49142a6534a998bef0c43529
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/395205
(cherry picked from commit 720c60aef1859b9c0d913c131203e02e6af4c3e6)
Reviewed-on: http://git-master/r/412607
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>
drivers/mmc/host/sdhci-tegra.c