ARM: tegra: clock: Keep CPU voltage above DFLL Vmin
authorAlex Frid <afrid@nvidia.com>
Tue, 23 Oct 2012 02:48:38 +0000 (19:48 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:40:12 +0000 (12:40 -0700)
commitd7795a4343bc819d038eba9ba48b68dab66533bc
treebeceb1f4bcd3af4021b2f26e109c72b0aff32a75
parent0b678f053c6bf4bd5258bff6edecf217a804b9ef
ARM: tegra: clock: Keep CPU voltage above DFLL Vmin

Updated DFLL On/Off procedures to keep CPU voltage above DFLL Vmin
during transition. This change is necessary now, as it is no longer
true that dvfs voltage in pll mode is above dfll mode voltage at all
rates.

Change-Id: I2bdc42998c745e06b8fa5b32395cf7b26c0bc1b4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147350
(cherry picked from commit 024210cfa6dd6173fe4edc4f0ed722a89ea370ce)
Reviewed-on: http://git-master/r/159411
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R9a7fcb7aa118ecc8bf51cf36836ac891bab25113
arch/arm/mach-tegra/tegra11_clocks.c