ARM: tegra11: power: Set safe cold voltage in DFLL mode
authorAlex Frid <afrid@nvidia.com>
Thu, 31 Jan 2013 22:52:01 +0000 (14:52 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:57:20 +0000 (12:57 -0700)
commitcf994bb45989e2d8c80c9b26f21d1f4b3404d72b
tree1b909e3550434639ac3674ec1008e56194ee5d11
parent5e98c877e9b66d05257af90d180b9b1e76aff69c
ARM: tegra11: power: Set safe cold voltage in DFLL mode

Used regulator API to set CPU voltage at cold temperature minimum
limit if DFLL is selected as fast G CPU clock source, and

- CPU is switching to LP cluster
- on entry to system suspend

This is done since in both cases: suspend and LP cluster operations,
CPU rail is off while temperature may go down, and on exit from each
state CPU will be running on DFLL clock for some time before CL-DVFS
regulation starts.

Change-Id: I02e06a2e92f348a147693ad2b811d7bedb4e70e2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196289
(cherry picked from commit fea89035708cc9f21f995194cb1586672e9c0e05)
Reviewed-on: http://git-master/r/199167
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arch/arm/mach-tegra/dvfs.c
arch/arm/mach-tegra/dvfs.h
arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra_cl_dvfs.c