ARM: tegra12: fix MC latency allowance programming
authorPeng Du <pdu@nvidia.com>
Wed, 19 Jun 2013 00:09:53 +0000 (17:09 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:29:08 +0000 (13:29 -0700)
commitc9f6d238211c52172bd0a453bad4a4dafa7f8d2b
treed1794149d56eac7b1a046d7634ef0a1429b3c9c2
parent1c5cb5fea8ac25db2ed2419fda7756bfb06262c1
ARM: tegra12: fix MC latency allowance programming

Unlike T3 and T114, MC latency allowance registers on T124+ are
not in a contiguous MMIO range anymore, which is fixed by this
change. This change also updated the latency allowance register
definitions based on T124's HW spec.

Bug 1289211

Change-Id: I225d1956f669c1efcebce0442856a8d28a692bef
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/242508
Reviewed-by: Adeel Raza <araza@nvidia.com>
Tested-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/common-t3.c
arch/arm/mach-tegra/mc-timing-t12x.c [new file with mode: 0644]
arch/arm/mach-tegra/mcerr.h
arch/arm/mach-tegra/tegra12_emc.h