ARM: tegra11: CPU rail power up sequence
authorBo Yan <byan@nvidia.com>
Mon, 7 May 2012 21:24:20 +0000 (14:24 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:11:14 +0000 (12:11 -0700)
commitc911d2ea1e1ce35b87e06c1d7954560577732f75
treed108be9d5ca60fbb10613f1ba243e86ec6bbebed
parent6d65d5bb0f0a20e9930de90b04a76ba5f7130ee9
ARM: tegra11: CPU rail power up sequence

It is necessary to disable RAM repair bypass when CPU rail is
powered up.  This needs to be done even in case of HW controlled
CPU rail power-on.

This change also enables cluster switch to use "power_gate" flag
defined in sysfs to control the power gating mode. For LP0 entry
case, rail-gating is set to default.

Set default power gating mode for cluster switch to rail gating.
For chips that doesn't support symmetric power gating, "0" is
the default value which will trigger rail-gating.

Change-Id: Ia7ccb023118bbfba4fa53dc263bdfda59e29f089
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/101045
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R50b64bfc236a664028edc822219af0d30d1af043
arch/arm/mach-tegra/pm-t3.c
arch/arm/mach-tegra/pm.h
arch/arm/mach-tegra/sleep.h
arch/arm/mach-tegra/sysfs-cluster.c
arch/arm/mach-tegra/tegra11_clocks.c