ARM: tegra11: Disable d-cache before power gating
authorBo Yan <byan@nvidia.com>
Wed, 25 Apr 2012 01:18:24 +0000 (18:18 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:10:58 +0000 (12:10 -0700)
commitbf241850a0e2bc4d639d1124d5b6948a1bbb4497
tree99bef7301a3e93acc9157bde40b779cb183ad516
parent508ac250a142aaee580d76f7c806cbaea4a5bd11
ARM: tegra11: Disable d-cache before power gating

For Cortex A15, the power down sequence requires D cache be
disabled before flushing cache and power gating the CPU.

bug 971396

Change-Id: I15c169c82780022877a0a49aa6403a9e5fd9d83f
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/98581
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R9af0f0af47ebb7260215b314cb958098a029183c
arch/arm/mach-tegra/hotplug.c