ARM: tegra: dvfs: Force CPU rail update
authorAlex Frid <afrid@nvidia.com>
Wed, 17 Oct 2012 03:08:56 +0000 (20:08 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:37:23 +0000 (12:37 -0700)
commitbabb00148380e39eacafd83ae04e914f9784ef18
treea3dd43f1966407490226fe7538c5c1cf56805477
parent453f9f01bd0c55adb204fbb51d9df471dc349d8e
ARM: tegra: dvfs: Force CPU rail update

To force CPU rail update on exit from DFLL mode:

- altered by 1mV recorded rail level in DFLL mode, so that it won't
match any target level after switch from DFLL to PLL (actual level
in DFLL mode is approximately close to the recorded, anyway)

- altered by 1mV maximum limit requested from regulator, so that
core regulator call is not resolved as NOP (tegra dvfs would not
call core API to set the same voltage, with the exception of special
cases like switch from DFLL - and in these cases we do not need core
second guess).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145168
(cherry picked from commit e18df75763f0d9f6980a2d77ed8e532afda4e96d)

Change-Id: I45271085bc1cdd9176a9a136b389292c6336ed35
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146288
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R3caa3cc159dc6280b67fed47226c592388ace835
arch/arm/mach-tegra/dvfs.c
arch/arm/mach-tegra/dvfs.h