Revert "clock: tegra21: Enable PLLE SS configuration"
authorSang-Hun Lee <sanlee@nvidia.com>
Sat, 20 Sep 2014 00:39:23 +0000 (17:39 -0700)
committerBharat Nihalani <bnihalani@nvidia.com>
Mon, 22 Sep 2014 04:13:32 +0000 (21:13 -0700)
commitba4c265f2e80da95a4fbfa6fadfb55c60ca7d80b
tree318b4567133113eac64ecacd355e7f4e99e9ef51
parent3ca94c75143478b4d192ad256e75d097fafeabcf
Revert "clock: tegra21: Enable PLLE SS configuration"

This reverts commit 200e9be3c3c9a11f29039cde4817e6849fde338c.

 - The above change prevents Foster HDD boot up

Bug 1556477

Change-Id: I9591ac9f54bacd967ebf5da6975e8e5390dd36a3
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/500964
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
drivers/platform/tegra/tegra21_clocks.c