ARM: tegra11: clock: Update switch to/from dfll clock source
authorAlex Frid <afrid@nvidia.com>
Wed, 19 Sep 2012 23:28:05 +0000 (16:28 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:37:00 +0000 (12:37 -0700)
commitac55cd0c8a47b2b7c9b490fd94390c5b42aef512
tree7b492517c1ee92c7a4c7c2179ca97ae68c4b7d1b
parent05171f18d6758b180b3cd59059a3872b0cf770e1
ARM: tegra11: clock: Update switch to/from dfll clock source

- Updated dvfs state variables and stats when switching to/from dfll
clock source.
- Made sure nominal voltage level is restored when switching from dfll
with disabled rail scaling.
- Round down target rate when switching from dfll to pll if it exceeds
pll mode maximum limit
- Implement 1-step dfll to pll switch directly to the new rate (instead
of 2-step switch from dfll to pll at the old rate, and then to the new
rate already on pll).

Change-Id: I13cfb89b47905cbc7c8b27a30cbc6472d4f651f3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/133969
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146245

Rebase-Id: R903d10b25c3552f368841e1f3de627dc7373fae3
arch/arm/mach-tegra/dvfs.c
arch/arm/mach-tegra/dvfs.h
arch/arm/mach-tegra/tegra11_clocks.c