ARM: tegra: power: Update DFLL bypass start/suspend/resume
authorAlex Frid <afrid@nvidia.com>
Fri, 2 Aug 2013 05:43:18 +0000 (22:43 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:39:19 +0000 (13:39 -0700)
commita98e68c16378962b11970a281857d943ddb5f294
tree952697a7524758eef2e4c6e96ddfcf400d634da0
parentdc117f3887970192282dfb78d3f9b0f40aee57ec
ARM: tegra: power: Update DFLL bypass start/suspend/resume

- Initialized DFLL before legacy dvfs if DFLL bypass is enabled
(reversed common initialization order: first legacy dvfs - then DFLL,
since  DFLL bypass device is used as regulator by legacy dvfs)

- Isolated DFLL output from voltage supply on entry to any state with
CPU cluster powered down (suspend, cluster idle), and resumed normal
operation on exit. This is necessary to avoid unpredictable effect of
DFLL output on CPU voltage during power transitions.

Bug 1310396

Change-Id: Ie42b92633367337ebc08200ab425baaf9043d133
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257346
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
arch/arm/mach-tegra/board-ardbeg-power.c
arch/arm/mach-tegra/clock.c
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/pm.h