ARM: tegra11: dvfs: Update CPU dvfs tables and bins
authorAlex Frid <afrid@nvidia.com>
Wed, 12 Dec 2012 05:19:04 +0000 (21:19 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:46:22 +0000 (12:46 -0700)
commita346f5ecd7fe5739a9fa15d451d9430479a1e641
tree09a40a3dac99dc451e57be597305d0c39e46cd6a
parentca5c1d893e764f46cee72a28bb107cf6afc127ab
ARM: tegra11: dvfs: Update CPU dvfs tables and bins

Based on characterization results:
- Integrated new cvb dvfs coefficients
- Expanded DFLL operating voltage range to 0.9V ... 1.35V with
  1.0V as dynamic tuning threshold
- Added speedo_id 2 to differentiate fast parts
- Duplicated CPU EDP table for new speedo_id

Bug 1170986
Bug 1178825
Bug 1161126

Change-Id: I49ccdb7c3d734dcdd3bb9f2542683d418d21ab5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170368
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arch/arm/mach-tegra/edp.c
arch/arm/mach-tegra/tegra11_dvfs.c
arch/arm/mach-tegra/tegra11_speedo.c