ARM: tegra: clock: Support restricted PLLM usage
authorAlex Frid <afrid@nvidia.com>
Sat, 12 Nov 2011 02:19:16 +0000 (18:19 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 07:58:13 +0000 (00:58 -0700)
commita094387586d44bd3b14358df98fb251dd377e286
tree8ee424e8ebb57edca998d4cb14fb51ec8807e33d
parent3b77c9fd5a0375d84cb06e7a70648442c75c0088
ARM: tegra: clock: Support restricted PLLM usage

Added configuration option TEGRA_PLLM_RESTRICTED - when enabled,
PLLM - memory PLL - usage may be restricted to modules with dividers
capable of dividing maximum PLLM frequency at minimum voltage. When
disabled, PLLM is available as a clock source with no restrictions
(current configuration), which may effectively increase lower limit
for core voltage if high grade SDRAM is used.

Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but
keep them disabled by default.

Bug 884419

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61)
(cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3)

Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa
Reviewed-on: http://git-master/r/66512
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Re70df2b753de37d6873609c121440337fc3ac626
arch/arm/mach-tegra/Kconfig