video: tegra: hdmi: choose clk rate above 100MHz
authorNaveen Kumar S <nkumars@nvidia.com>
Wed, 20 Jul 2016 11:17:05 +0000 (16:17 +0530)
committerMatthew Pedro <mapedro@nvidia.com>
Tue, 26 Jul 2016 16:43:08 +0000 (09:43 -0700)
commit9a1e9a92e975274f4b3507922b7ab4805defe975
tree564f621fa131072e6b0824411baa2e7e3dfc7de0
parenta7da876159f2b71ad411c31d08030be2e99dd417
video: tegra: hdmi: choose clk rate above 100MHz

pll_d2 runs at a minimum of 100MHz on T124. Update logic
to choose parent clock rate more than 100MHz.
e.g.: A mode with 32MHz pclk chooses parent clock of
96MHz with a divider of 3.0, which fails as pll_d
can't be pulled below 100MHz.

bug 1785365

Change-Id: I12400549a3ed42295ddd46adcb6493232f2d896a
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/1184235
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
drivers/video/tegra/dc/hdmi.c