PCIE: tegra: resume timing correction
authorBibek Basu <bbasu@nvidia.com>
Tue, 29 Apr 2014 09:11:31 +0000 (14:11 +0530)
committerWinnie Hsu <whsu@nvidia.com>
Thu, 8 May 2014 23:40:08 +0000 (16:40 -0700)
commit985da60bc44a06804c739b1b699b9826bbeb8a94
tree6dcf6ee0b3f1779cedf09b2965e35e10225f6d5b
parent39a8dd91677d732a0cce2b02cb697c43a2407789
PCIE: tegra: resume timing correction

The time from +1.05V_RUN to PEX_L1_RST_L signal
(PEX_L1_RST_N on T124) should be 100ms minimum

Bug 1500840

Change-Id: I170ed3225f80b5ef0ccaf4b38565d3adf94a674a
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/402841
(cherry picked from commit d380528e5e865437681c21befc40de430b39f9a9)
Reviewed-on: http://git-master/r/406394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
drivers/pci/host/pci-tegra.c