tegra: T124: HDMI: fix pixel clock setting
authorJong Kim <jongk@nvidia.com>
Thu, 27 Mar 2014 16:18:58 +0000 (09:18 -0700)
committerWinnie Hsu <whsu@nvidia.com>
Sat, 5 Apr 2014 02:19:17 +0000 (19:19 -0700)
commit924c271030498d9bc9763bea4fa83875e1125632
treea1523d782bf4165e7fd46adef66db9d6801a60cd
parent45788437a0172066ad6c70de24be06390a04ad68
tegra: T124: HDMI: fix pixel clock setting

- Enhance the HDMI pixel clock setting by determining a better parent
  clock rate.  Half resolutions for HDMI pclk are not used due to
  uneven duty cycle.
- Fix the divider value out of sync problem between two registers,
  DISP_DISP_CLOCK_CONTROL and CLK_RST_CONTROLLER_CLK_SOURCE_HDMI, due
  to the rounding difference.  The clk_set_rate() routine uses round-up,
  while the tegra_dc_program_mode() routine uses round-closest.  Due to
  the DVFS, the frequency determination can not exceed the requested
  rate and this means that round-up must be used for divider handling
  instead of round-closest.

bug 1420652

Change-Id: Ib32e79f96dcd272a392de7f852c3c0285f9c453a
Signed-off-by: Sungwook Kim <sungwookk@nvidia.com>
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/366390
(cherry picked from commit 6eb5d7e7b5dcd9a118649e5a8d02e35cf45a4fc6)
Reviewed-on: http://git-master/r/392419
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
drivers/video/tegra/dc/clock.c
drivers/video/tegra/dc/hdmi.c
drivers/video/tegra/dc/mode.c