ARM: tegra: ardbeg: SDMMC4 ddr trim,clk limits
authorPavan Kunapuli <pkunapuli@nvidia.com>
Wed, 3 Jul 2013 14:00:43 +0000 (07:00 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:29:51 +0000 (13:29 -0700)
commit8f2ad3fe2a0f74d9d4cc3a641202d38a83232783
tree3874245d911f314ae6bb197e521b60d3bf866da7
parent79be341fe319854595e52ba0dba075c8007e4abc
ARM: tegra: ardbeg: SDMMC4 ddr trim,clk limits

Set DDR50 mode trim delay to 0x4. Also, set the ddr mode and
default mode clock limits for sdmmc4.

Change-Id: I79047c805f7c6ebc66100382199e2778e77675dd
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/244769
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
arch/arm/mach-tegra/board-ardbeg-sdhci.c