ARM: tegra14x: Support BB-aware LP1
authorPrashant Malani <pmalani@nvidia.com>
Mon, 25 Feb 2013 21:11:44 +0000 (13:11 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:01:35 +0000 (13:01 -0700)
commit880be110ea946ea94d102827d1bc170caed1246c
treefbfa6ba46227827ccfb188fea5da00bdce1ae255
parent0ce824cf43ba8b0c448d0224dfa36def13daf65a
ARM: tegra14x: Support BB-aware LP1

This enables LP1 exit due to BB paging event.
In case we enter LP1, mem_req=1 is set as the
wake event.

This allows LP1BB to be entered even when a
legacy LP1 entry is triggered.

Bug 1239689

Change-Id: Ia9ae305eb1bf3923e261d4e5c67b2c4db7b6b07e
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/203969
(cherry picked from commit 52b5885d344d6d17067658c6fd382bbee73b54ca)
Reviewed-on: http://git-master/r/204900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
arch/arm/mach-tegra/sleep-t30.S