ARM: tegra11: Update cache flush/invalidate for power gating
authorBo Yan <byan@nvidia.com>
Sat, 19 May 2012 02:38:05 +0000 (19:38 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:11:34 +0000 (12:11 -0700)
commit7d7c3999aaa232e88fb84ce5aadb349d690dae6f
tree6429d6d0a1c9951c5a5e95f2537a5cde24f61c80
parent1315663a4c31e09b6565d2b8185980dab938e6b1
ARM: tegra11: Update cache flush/invalidate for power gating

The field ENABLE_EXT in CSR register controls what power partition
to be gated. If it's CPU-partition power gating only, there is no
need to flush or invalidate L2 cache before/after power gating.
With this change, L2 cache is flushed/invalidated only when the
non-CPU partition is to be power gated or when rail gating is
selected.

Change-Id: I6be522de694117a058eedc9584f2157d89f99dc4
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103476
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: R3108cb94a1efc64574ff58067e239bd8539e6059
arch/arm/mach-tegra/headsmp.S
arch/arm/mach-tegra/sleep-t20.S
arch/arm/mach-tegra/sleep-t30.S
arch/arm/mach-tegra/sleep.S