arm: tegra: pm: add delay between writes to IO_DPD_REQ
authorJay Cheng <jacheng@nvidia.com>
Fri, 16 May 2014 21:13:10 +0000 (17:13 -0400)
committerRiham Haidar <rhaidar@nvidia.com>
Fri, 13 Jun 2014 00:33:25 +0000 (17:33 -0700)
commit7bd24037512399b542a735aa45c7ded89143cc86
tree5b04bfddf3542ebe22307a71c906559591fb9af7
parent978e7e53c9b82d78026b69fd18475d7d9dcb7a17
arm: tegra: pm: add delay between writes to IO_DPD_REQ

SW should explicity add delay between writes to IO_DPD_REQ and
IO_DPD2_REQ registers. This is because we use the same state machine
for both the registers.

The time between writes should be apb clk * (SEL_DPD_TIM + 5).
The worse case of apb clk is 32Khz,
SEL_DPD_TIM is configured as 0x10.
delay = (1/32000) * (16 + 5) which approximately 700us.

Bug 200002717

Change-Id: Icf4efdbc38ccdaca30a9d86da488ac796b657b36
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
Reviewed-on: http://git-master/r/411065
(cherry picked from commit ebba7445ff9a32af6bb1759ac70311f66e2986cb)
Reviewed-on: http://git-master/r/412826
Reviewed-on: http://git-master/r/418379
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
arch/arm/mach-tegra/pm.c
drivers/platform/tegra/pmc.c