mmc: tegra: Parse dt node for max clk, uhs mask
authorPavan Kunapuli <pkunapuli@nvidia.com>
Wed, 26 Jun 2013 12:53:14 +0000 (17:53 +0530)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:29:16 +0000 (13:29 -0700)
commit76e5c777e44cc35ec143790fdd0ad6018abedd55
treed324ddbd6af71ba7d89e01e81540736316cd49a7
parentdb4d03737191871daa5c3b380e6543177171964a
mmc: tegra: Parse dt node for max clk, uhs mask

Add supporting for parsing dt node to get the max clk limits and
the uhs mask data.
Base clock frequency is fixed for each instance of controller and need
not be programmed. Removed base clk parsing code.

Bug 1314985

Change-Id: Iab9b6014557738ac66a58168458130e6f8e47e4f
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/242433
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
drivers/mmc/host/sdhci-tegra.c
include/linux/platform_data/mmc-sdhci-tegra.h