media: tegra_v4l2_camera: set clock rate for pll_d
authorBryan Wu <pengw@nvidia.com>
Wed, 27 Aug 2014 23:31:13 +0000 (16:31 -0700)
committerWinnie Hsu <whsu@nvidia.com>
Fri, 26 Sep 2014 17:49:50 +0000 (10:49 -0700)
commit746183c0038fa0338ad2ac3fb3ec1b9ebe909af8
treeabf7f8b0ae2e58d7f139b3f66f15d8862590db7b
parent31036901c622408e6b12be1740f781bc261ff4ee
media: tegra_v4l2_camera: set clock rate for pll_d

Test pattern generator in VI needs PLL_D running at certain clock
rate, then CSI clock is a child of PLL_D can get the right clock
for operation.

If DC disable DSI and set PLL_D as a very low frequency and VI driver
forgets to set PLL_D rate back, test pattern generator won't work.

This patch will set PLL_D as 927M when we do test pattern generator
testing.

Bug 1515755

Change-Id: I8fd27d193a436e1057ce2bce8f8153630dc5cdce
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/489043
(cherry picked from commit e09393ad2a02309f63a3baeb567460e1e2f79cd9)
Reviewed-on: http://git-master/r/498938
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
drivers/media/platform/soc_camera/tegra_camera/vi2.c