ARM: tegra11: dvfs: Update switch between DFLL and PLL
authorAlex Frid <afrid@nvidia.com>
Tue, 12 Feb 2013 19:04:40 +0000 (11:04 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 20:00:14 +0000 (13:00 -0700)
commit73bdee72cabf153b089dff907509a47621c72901
treef9e38a2d67897d55a7519aa36fa5d09a8360ac4d
parent5868c14d425ad5cd6c826039ac09fcf311950bf5
ARM: tegra11: dvfs: Update switch between DFLL and PLL

Modified procedures for auto-switching between PLL and DFLL CPU clock
sources.

- On switch from PLL to DFLL do not allow legacy DVFS to set voltage
for target rate in one shot. Limit setting to minimum DFLL voltage,
and let DFLL to complete voltage ramp after the switch.

- Similarly on switch from DFLL to PLL, first use DFLL mode to lower
cpu voltage to DFLL minimum, leaving only delta down to target for
legacy DVFS.

This modifications speed up the transitions and make them safer, since
major change of voltage, rate, and consumed current happens in DFLL
mode.

Change-Id: I42eee166510bd74d046bc6b3cb232ca10233ead9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/200382
(cherry picked from commit 4a0c6ef45d3f806835c27fc492a09e2eb254b0a6)
Reviewed-on: http://git-master/r/203613
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arch/arm/mach-tegra/dvfs.c
arch/arm/mach-tegra/dvfs.h
arch/arm/mach-tegra/tegra11_clocks.c