ARM: tegra11x: remove redundant cpu invalidation
authorBo Yan <byan@nvidia.com>
Tue, 13 Nov 2012 17:59:01 +0000 (09:59 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 14 Sep 2013 19:42:57 +0000 (12:42 -0700)
commit73519fe7eb4799d31aab891dedd6c50b0f650bdb
tree1736fac2bd72d300f5cf0ffaff8b7f8fe3538eda
parenta744883c4643f28c3e977660d180e946cecccc7f
ARM: tegra11x: remove redundant cpu invalidation

This is a follow up to commit 49de51f9. During a processor reset,
following memory arrays in the processor are invalidated at reset:

  branch prediction arrays such as BTB, GHB, and indirect predictor.
  L1 instruction and data TLBs
  L1 instruction and data caches
  L2 unified TLB

So remove instructions invalidating memory arrays identified above.

Change-Id: Id933867d68b7813c5e47ed05da8e855888f8d959
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/163285
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
arch/arm/mach-tegra/headsmp.S