mmc: tegra: Fix parent clk configuration
authorPavan Kunapuli <pkunapuli@nvidia.com>
Fri, 28 Mar 2014 11:43:24 +0000 (16:43 +0530)
committerPavan Kunapuli <pkunapuli@nvidia.com>
Mon, 14 Apr 2014 10:54:55 +0000 (03:54 -0700)
commit720c60aef1859b9c0d913c131203e02e6af4c3e6
tree4e4f0527d082cd416ab9a60f5401109f217d8c1b
parent73687a8eb4734170f7451f08dcf865bd5b494a8a
mmc: tegra: Fix parent clk configuration

Do not ignore parent clk setting and parent clock source flag
update for any case. For eMMC, in resume, without pll_c as clk
source, 200MHz cannot be set in HS200 mode set.

Bug 1480583

Reviewed-on: http://git-master/r/389704
(cherry picked from commit b9b0cb1541d66ba2450a680666c3fe962b4f71df)

Change-Id: I7898a57871cd16de49142a6534a998bef0c43529
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/395205
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
drivers/mmc/host/sdhci-tegra.c